Patents Assigned to Akita Electronics Co., Ltd.
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Patent number: 6262488Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.Type: GrantFiled: April 16, 1999Date of Patent: July 17, 2001Assignees: Hitachi Ltd., Hitachi Tobu Semiconductor, Ltd., Akita Electronics, Co., Ltd.,Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
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Patent number: 5910685Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.Type: GrantFiled: December 3, 1997Date of Patent: June 8, 1999Assignees: Hitachi Ltd., Hitachi Tobu Semiconductor, Ltd., Akita Electronics, Co., Ltd.Inventors: Masayuki Watanabe, Toshio Sugano, Seiichiro Tsukui, Takashi Ono, Yoshiaki Wakashima
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Patent number: 5708298Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.Type: GrantFiled: December 10, 1996Date of Patent: January 13, 1998Assignees: Hitachi Ltd., Hitachi Tobu Semiconductor, Ltd., Akita Electronics, Co., Ltd.Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
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Patent number: 5614860Abstract: A voltage-controlled filter circuit has a cutoff frequency directly proportional to a ratio of two current values. The filter circuit comprises a variable conductance circuit having two bipolar junction input transistors supplied with an input voltage signal at the bases thereof and a first variable current source at each emitter thereof. The collectors supply the bases of a pair of differential transistors. A second variable current supply is coupled to common emitters of the pair of differential transistors. Externally supplied control signals set the two current values of the variable current sources. The filter circuit may be manufactured as a semiconductor integrated circuit device for signal processing for use in processing a recorded signal read from a recording medium. The recorded signal is supplied to a semiconductor integrated circuit for signal processing to remove unwanted signal and noise components.Type: GrantFiled: April 26, 1995Date of Patent: March 25, 1997Assignees: Hitachi, Ltd., Akita Electronics Co., Ltd.Inventors: Katsumi Osaki, Takashi Nara, Hitoshi Watanabe
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Patent number: 5587341Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.Type: GrantFiled: October 18, 1994Date of Patent: December 24, 1996Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor, Ltd., Akita Electronics Co., Ltd.Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
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Patent number: 5285168Abstract: An operational amplifier is equipped at its input stage with a folded cascode type differential amplifier and at its downstream stage with pre-buffers, which include a differential amplification stage of PMOS input and a differential amplification stage of NMOS input, as level shifters. A MOS resistor having its gate terminal fed with an intermediate bias potential between a supply voltage V.sub.DD and an earth potential is connected between every one of the drain terminals of current-mirror connected load MOSFETs in the pre-buffers. As a result, the gains of the pre-buffers in the steady state can be suppressed to about 10 dB or less. The individual MOSFETs of the push-pull output stage are individually driven by the pre-buffers of low gains.Type: GrantFiled: September 15, 1992Date of Patent: February 8, 1994Assignees: Hitachi, Ltd., Akita Electronics Co., Ltd.Inventors: Takashi Tomatsu, Takaaki Noda
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Patent number: 5138438Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.Type: GrantFiled: November 25, 1991Date of Patent: August 11, 1992Assignees: Akita Electronics Co. Ltd., Hitachi Ltd., Hitachi Semiconductor Ltd.Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
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Patent number: 5068828Abstract: A semiconductor memory device having a plurality of memory arrays in which static memory cells are disposed in a lattice arrangement at intersections of word lines and complementary data lines. The load circuits thereof are characterized as having a varying impedance effected by the combination of a first pair of P-channel MOSFETs disposed between the complementary data lines and a first node supplied with a first supply voltage and kept normally in an ON-state, and a pair of transistors, such as a second pair of P-channel MOSFETs, similarly connected as the first pair of P-channel MOSFETs and which are turned off selectively in accordance with a control signal corresponding to a predetermined selection timing signal in a write-in mode. The semiconductor memory device has a plurality of switching circuits which are coupled between the plurality of complementary data lines and a pair of data read and write lines.Type: GrantFiled: June 19, 1990Date of Patent: November 26, 1991Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering, Ltd., Akita Electronics Co., Ltd.Inventors: Shuuichi Miyaoka, Masanori Odaka, Toshikazu Arai, Hiroshi Higuchi
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Patent number: 4984058Abstract: In a semiconductor integrated circuit device having memory cell arrays, power source wirings are provided on the memory cell array in parallel with the long side of the memory cell array, thereby strengthening the power source wirings without increasing a chip size and planning reduction in power source impedances.Type: GrantFiled: July 28, 1988Date of Patent: January 8, 1991Assignees: Hitachi Microcomputer Engineering, Ltd., Hitachi, Ltd., Akita Electronics Co., Ltd.Inventors: Shuuichi Miyaoka, Nobuo Tamba, Toshikazu Arai, Hiroshi Higuchi, Hisayuki Higuchi
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Patent number: 4982265Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.Type: GrantFiled: June 22, 1988Date of Patent: January 1, 1991Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor, Ltd., Akita Electronics Co., Ltd.Inventors: Masayuki Watanabe, Toshio Sugano, Seiichiro Tsukui, Takashi Ono, Yoshiaki Wakashima
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Patent number: 4961164Abstract: A semiconductor memory device is provided which includes a plurality of memory arrays each including main word lines, sub word lines to which a plurality of memory cells are connected, and a decoder which selectively connects the sub word lines to the main word lines. The main word lines are relatively short, since they are isolated electrically between memory arrays, and their resistance can thus be relatively low. The main word lines are not directly connected with a plurality of memory cells, and this results in a smaller capacitance coupled to the main word lines than is customarily the case. Consequently, the semiconductor memory device can have an enhanced operating speed.Type: GrantFiled: October 31, 1989Date of Patent: October 2, 1990Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering, Akita Electronics, Co., Ltd.Inventors: Shuuichi Miyaoka, Masanori Odaka, Hiroshi Higuchi, Toshikazu Arai
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Patent number: 4935898Abstract: A semiconductor memory device having a plurality of memory arrays composed of mutually orthogonal row word lines and complementary column data lines, and static memory cells disposed in a lattice arrangement at the intersections of such word lines and complementary data lines; variable impedance load circuits having first P-channel MOSFETs disposed between the complementary data lines and a first supply voltage and kept normally in an on-state, and also having second P-channel MOSFETs connected in parallel with the first P-channel MOSFETs and cut off selectively in accordance with predetermined selection timing signals in a write mode; a plurality of signal generator circuits provided correspondingly to the memory arrays for forming the selection timing signals in accordance with write control signals and array selection signals, and then feeding the timing signals to the corresponding variable impedance load circuits; and a plurality of signal relay circuits provided correspondingly to a predetermined numberType: GrantFiled: August 4, 1988Date of Patent: June 19, 1990Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering, Ltd., Akita Electronics Co., Ltd.Inventors: Shuuichi Miyaoka, Masanori Odaka, Toshikazu Arai, Hiroshi Higuchi