Abstract: A single layer copper foil tape is provided having a center core and connected lead beams. Etched apertures are formed to separate adjacent lead beams and to form relatively high strength foil straps connecting edge portions of the foil tape and the center core. Score lines may be etched at the ends of each of the lead beams to form breakaway links at such ends. The inner ends of the lead beams are then bonded to a semiconductor die at its contact pad or bumps and the resultant subassembly aligned with inner ends of the fingers of a metal lead frame array or other set of external leads such as a pin grid array and the outer ends of the lead beams bonded to such fingers. At this point, all of the remaining portions of the foil tape are peeled or pulled off the assembly, the lead beams being separated at their breakaway links, leaving only the lead beams connecting the die and set of external leads intact.

Abstract: Desired control of the thickness and composition of a solder coat on the J-leads of an integrated circuit Quad package is obtained by orienting the packages while being solder coated in a "leads-up" orientation as a series of strips mounting the packages are passed through a solder wave of a wave soldering apparatus on a pallet. The Quad or other shaped integrated circuit or other electronic packages which have leads extending exteriorly thereof, thus have the critical lead crest portions coated with substantially the same solder layer thickness and composition. This permits reliable electrical connections between the crest portions of the leads and printed circuit board metal traces (metallization), particularly in surface mounting of the package to a printed circuit board. An additional feature of the invention is a pallet for holding a series of package-holding elongate frames which pallet is used for conveying the packages through the wave soldering apparatus.

Abstract: A unique driver circuit for providing constant average current through a driven element or elements having varying impedance first samples the impedance at the drive terminal in order to determine impedance of the driven elements. For increasing impedance of the driven elements, the duty cycle of the driving signal is increased, thereby resulting in a near-constant average current through the driven elements when the number of driven elements in series is changed.

Abstract: The addresses of firmward (ROM) being interrogated to ascertain data are continuously monitored. Selected key addresses are recognized by address detection means. Timing means is then actuated to count a preset number of address accesses, system clock cycles, or other suitable timing means. A substitute address is provided to the firmware when the timer counts down. If the incoming address is in the correct sequence then the substituted address will be the same as the incoming address and correct data will be provided by the ROM. Otherwise, incorrect data will be provided. Alternately, after countdown the incoming address can be compared with the expected incoming address. If the comparison indicates identity then the incoming address can be supplied to the firmware. Otherwise, an incorrect substitute address can be provided to the input of the firmware or incorrect substitute data can be provided on the output of the firmware.

Abstract: The present apparatus provides for the encoding of data carried on bus lines running between integrated circuits in order to protect the data carried upon those bus lines, with encoding and decoding circuits included for providing those functions in regard to the data on the bus lines.

Abstract: An encoding interface is provided between input data ports and strobe output ports of a (semiconductor integrated) circuit (chip) and an array of switches (40) is connected to a series of L input data lines and output lines (31-38), whereby the L lines can alternatively strobe the switch matrix to determine the (50) position of each switch. By having each line function either as an input line or an output line at a particular instant of time, the number of switches being served by a fixed number of total input and output lines is increased. For example, with eight total lines 28 switches are accommodated when the lines function either as input or output lines while when four separate lines are dedicated as input lines and four other lines dedicated as output lines only 16 switches are accommodated. In a further embodiment using two switches and a pair of oppositely disposed diodes at each cross point in the matrix the number of switches can be doubled (to 56 with eight dual input/output lines).

Abstract: Desired control of the thickness and composition of a solder coat on the J-leads of an integrated circuit Quad package is obtained by orienting the packages while being solder coated in a "leads-up" orientation as a series of strips mounting the packages are passed through a solder wave of a wave soldering apparatus on a pallet. The Quad or other shaped integrated circuit or other electronic packages which have leads extending exteriorly thereof, thus have the critical lead crest portions coated with substantially the same solder layer thickness and composition. This permits reliable electrical connections between the crest portions of the leads and printed circuit board metal traces (metallization), particularly in surface mounting of the package to a printed circuit board. An additional feature of the invention is a pallet for holding a series of package-holding elongate frames which pallet is used for conveying the packages through the wave soldering apparatus.

Abstract: A circuit constructed in accordance with this invention is described which includes a programmable chip enable-output enable buffer (11-X). The chip enable-output enable buffer may be programmed to provide a chip enable function in response to a logical 1 or logical 0 chip enable input signal, an output enable function in response to a logical 1 or logical 0 output enable input signal, or an active powered chip regardless of the provided input signal. The chip enable-output enable buffer is programmed by "programming" selected transistors in the buffer. A P channel transistor (40, 60) is programmed by causing its source to be connected to its drain. An N channel transistor (50, 60) is programmed by causing its source and drain to be disconnected. In one embodiment, the programming is accomplished in the preferred embodiment by either a diffusion process or an ion implantation process.

Abstract: A unique method and structure is provided for testing high voltage equipment with great accuracy of voltage levels to be measured, repeatability of measured levels from one piece of test equipment to the next, no need for recalibration of test equipment, and sufficiently low current during testing that the test equipment can be powered by the same supply that powers the device under test. The device of this invention can be used to measure not only logical one and logical zero voltage levels of the device under test while under specific loads but can also be used to meausre transition time from one logic state to another.The circuit of this invention provides an output signal which can have three states reflecting a high logic level from the device under test, a low logic level from the device under test, and an intermediate level indicating that the device under test is in transition from one logic level to another or has failed the test.

Abstract: Voltage controlled oscillator (50) provides an exponential transfer function. The frequency of the output signal of the voltage controlled oscillator varies exponentially with the input voltages (V.sub.IN1, V.sub.IN2) to the oscillator. The exponential transfer characteristic is provided by means of a MOS field effect transistor (19) biased in its subthreshold range.

Abstract: A matrix comprised of pass transistor cells (81 through 96) forms an address decoder circuit (80). By using pass transistor cells in a matrix format, a decoder which consumes a minimum of power and which may be constructed using a minimum of allotted space in an integrated circuit is achieved.

Abstract: A circuit (40) is capable of receiving a very high voltage input signal, for example from a piezoelectric transducer (1). The circuit accepts the relatively large input voltage of the piezoelectric transducer (1) and provides an output signal proportional to the square root of the input voltage.

Abstract: A flip-flop stores input data on both the leading and trailing edges of a clock pulse. The flip-flop includes a data path responsive to the leading edge of a clock pulse and a second data path responsive to the trailing edge of a clock pulse, thereby allowing data to be stored on both the leading edge and the trailing edge of a clock pulse.

Abstract: PASS transistors are used to reduce the layout complexity of logic circuits by using PASS transistors connected to pass a first and second input function to an output node in response to selected control signals, thereby to generate a selected output function on the output node. The PASS transistor comprises a transistor capable of passing an input function in response to a control signal applied to the transistor thereby to generate an output function related to the input function. In general, the input function comprises less than all of a set of input variables and the control function comprises one or more of the remainder of the set of input variables.

Abstract: A unique frequency doubler circuit is utilized which requires only a handful of standard components such as operational amplifier, logic gates, resistors, capacitors and switches. In contrast to certain prior art frequency doublers, frequency doublers constructed in accordance with the teachings of this invention do not require the use of a phase lock loop, thereby resulting in a substantial simplification of circuit construction. Furthermore, frequency doublers constructed in accordance with this invention utilize a feedback technique which assures that the duty cycle of the output signal will be 50%, or any other predefined value.

Abstract: An integrated circuit digital to analog converter comprised of MOS current mirrors and utilizing additional MOS devices to provide transmission gates and control means. Each transmission gate 36 is connected to a source of digital data to be converted and the mirroring device for each transmission gate 36 has a channel width with some predetermined proportional relationship to the channels of input transistors 12 and mirroring output MOS transistors 14 to 44 with the input transistor 12 connected to a constant current source, the total output mirroring current of the output mirroring transistors is in quantised analog form and varies according to the cumulative currents from the mirroring MOS transistors as the transistors are activated. The invention may be embodied in linear multiplying, non-linear and companding converters.

Abstract: A pulse width digital to analog converter is constructed which provides an output clock rate that is a multiple of the input sampling rate. In one embodiment a latch is used to store N-bit digital word representing the analog signal value to be generated. (N-K) of the most significant bits are stored in a counter which decrements its count in response to a clock signal. A plurality of least significant bits of said digital word stored in said latch are applied to a logic circuit. A ring counter is utilized to indicate which section of the output signal is currently being generated.

Abstract: A phase locked loop circuit (16) includes means to eliminate harmonic frequency locking. The phase locked loop includes a voltage controlled oscillator (1) which provides an output signal (V.sub.out) which is compared with the input signal (V.sub.in) by a phase detector (4). The output signal from the phase detector is integrated and the output signal of the integrator (7) is placed on the control input lead of the voltage controlled oscillator. The output signal of the voltage controlled oscillator is provided to a frequency detector (14, 17) which determines if the output frequency is within a predefined range. If the output frequency is above the predetermined range, a limiter circuit (15) provides a low voltage output signal to the control input lead of the VCO in order to pull the input voltage of the VCO to a voltage which corresponds with the appropriate operating range of the phase locked loop.

Abstract: A single-shot circuit is fabricated as an integrated circuit except for a single capacitor requiring a single pin to connect to the on-chip circuitry. The single-shot is rendered independent of process variations and operating conditions by incorporating an analog feedback loop. The output of the single shot is detected by an analog circuit which includes a positive and negative voltage generator the ratio of whose voltages is a function of the desired duty cycle. The generators are actuated, respectively, when a pulse exists and when there is no pulse. The analog feedback circuit also includes an integrator for receiving and integrating the positive and negative voltages from the generators. The integrated and amplified voltages are fed back to the last stage of the single-shot circuit. When the duty cycle is high, the voltage that is fed back drives the single shot circuit to reduce the pulse width.

Abstract: PASS transistors are used to reduce the layout complexity of logic circuits by using PASS transistors connected to pass a first and second input function to an output node in response to selected CONTROL signals, thereby to generate a selected output function on the output node. The PASS transistor comprises a transistor capable of passing an input function in response to a CONTROL signal applied to the transistor thereby to generate an output function related to the input function. In general, the input function comprises less than all of a set of input variables and the CONTROL function comprises one or more of the remainder of the set of input variables.