Abstract: An active electronic steered antenna (AESA) circuit monitors bursts of a phased array that has a plurality of signal chains. Each signal chain therefore has a burst output for transmitting at least one burst. To monitor bursts, the AESA circuit has an input that is operably couplable with the burst output of at least one signal chain of the phased array. The input is configured to receive one or more bursts transmitted by the burst output(s) of the at least one signal chain. The AESA circuit also has a sample circuit operably coupled with the input and configured to sample the one or more bursts to produce one or more corresponding samples, and memory operably coupled with the sample circuit. The memory receives and stores the one or more samples. To provide access to the samples, the AESA circuit also has a memory interface.

Abstract: A circuit for attenuating a signal has an input configured to receive an input signal, an output configured to transmit an output signal, a first attenuation path (having a first active circuit device) between the input and the output, and a second attenuation path between the input and the output. The circuit also has an operational amplifier that, like most operational amplifiers, has a first op-amp input, a second op-amp input, and an op-amp output. In addition, the circuit has a voltage control device coupled with the first op-amp input, and a second active circuit device having a first active terminal coupled with the second op-amp input. A feedback loop is coupled between the op-amp output and a second active terminal of the second active circuit device. Moreover, the op-amp output also is coupled with the first active circuit device.

Abstract: A phased array has a laminar substrate, a plurality of elements on the laminar substrate forming a patch phased array, and first and second sets of integrated circuits on the laminar substrate. The first set of integrated circuits, each of which are single polarity integrated circuits, connects with a first set of the plurality of elements, and are configured to operate using first signals having a first polarity. In a similar manner, each one of the second set of integrated circuits also is a single polarity integrated circuit and connects with a second set of the plurality of elements. Also, each of the second set of integrated circuits is configured to operate using second signals having a second polarity. The first polarity is substantially orthogonal to the second polarity (i.e., to not interfere with each other).

Abstract: In certain exemplary embodiments, register banks are used to allow for fast beam switching (FBS) in a phased array system. Specifically, each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be preprogrammed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Additionally or alternatively, active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.

Abstract: A laminar phased array has a plurality of receive elements and dual transmit/receive elements supported on a substrate. The plurality of receive elements and dual transmit/receive elements form a patch array across the substrate. As such, the receive elements and dual transmit/receive elements form an array of patch antennas on the substrate. The phased array also has a plurality of integrated circuits supported on the substrate. At least a first set of the plurality of integrated circuits is configured to control receipt of signals by the receive elements. In a corresponding manner, at least a second set of the plurality of integrated circuits is configured to control receipt and transmission of signals by the dual transmit/receive elements.

Abstract: In some example implementations, there may be provided methods for beamforming calibration of active electronically steered arrays (AESA). In some implementations, one or more adders may generate a phase offset by adding phase calibration data from non-volatile memory and phase command data from static memory, and/or generate a gain offset by adding gain calibration data from the non-volatile memory and gain command data from the static memory. Further, a phase-shift circuit can modify, based on the phase offset, a phase of a first output signal, and an amplitude gain circuit can modify, based on the gain offset, an amplitude of the first output signal. In accordance with these implementations, the modified phase of the first output signal and the modified amplitude of the first output signal are provided to enable pre-calibration of the first output signal and/or a first antenna. Related systems, methods, and articles of manufacture are also described.

Abstract: An apparatus may include a plurality of antenna elements forming an antenna array. The apparatus may further include a beamformer that determines one or more of phase and amplitude shifts to cause the plurality of antenna elements to produce a beam in the direction of a target. The apparatus may further include a null limiter comprising dither circuits. The dither circuits may dither the one or more of phase and amplitude shifts by adding noise to cause a side lobe of the beam to increase above a threshold value. The dither circuits may be enabled by a control signal, and the dithered one or more of phase and amplitude shifts may be provided to the antenna elements to produce the beam in the direction of the target with the side lobes above the threshold value.

Abstract: A beamforming integrated circuit has a single channel with a transmit chain and a receive chain. The transmit chain is configured to transmit an output signal and, in a corresponding manner, the receive chain is configured to receive an input signal. The integrated circuit also has separate horizontal and vertical polarity ports, and a double pole, double throw switch operably coupled between the chains and the ports. The double pole, double throw switch is configured to switch between operation in a first mode and a second mode.

Abstract: In some example implementations, there may be provided methods for beamforming calibration of active electronically steered arrays (AESA). In some implementations, one or more adders may generate a phase offset by adding phase calibration data from non-volatile memory and phase command data from static memory, and/or generate a gain offset by adding gain calibration data from the non-volatile memory and gain command data from the static memory. Further, a phase-shift circuit can modify, based on the phase offset, a phase of a first output signal, and an amplitude gain circuit can modify, based on the gain offset, an amplitude of the first output signal. In accordance with these implementations, the modified phase of the first output signal and the modified amplitude of the first output signal are provided to enable pre-calibration of the first output signal and/or a first antenna. Related systems, methods, and articles of manufacture are also described.

Abstract: A packaged IC has a package with a die paddle, a signal lead, and a ground lead. The packaged IC also has a die, secured to the package, with a ground pad and a signal pad. The signal pad is electrically connected to the signal lead, and the ground pad is electrically connected to both the die paddle and the ground lead.

Abstract: Methods, apparatuses, computer program products, and computer readable media are disclosed herein. In one aspect, an apparatus can include a transmission line configured to accept a radio frequency signal from an antenna, wherein the antenna is configured to receive the radio frequency signal from a satellite. The apparatus can further include a system on a chip comprising a direct conversion receiver, a digital signal processor configured to process a digital representation of a baseband receive waveform to determine received information, and a wireless networking interface configured to send the received information to a satellite communications indoor unit.

Abstract: A circuit arrangement for assigning identification address to each element of an array of elements of a phased array, or assigning a unique digital word to a isolated circuit. In one embodiment two external resistors are used to provide an analog voltage. That voltage can be converted to digital word and stored in a chip using latches and registers. The stored digital word can then be use as address for the army element used in phased array. Thereby access to the array element can achieved using the address as a header of a digital bit stream.

Abstract: Two or more transceiver units can interact with each other via millimeter wave radio frequency signals. One of the transceiver units can detect time-varying signals having specific waveforms in order to initiate an action such as establishment of a communication link, powering a piece of equipment and the like. The time-varying signal can be generated by a user moving one of the transceiver units and/or by passing an non-transmissive obstruction in between the transceiver units. Related apparatus, systems, and methods are also disclosed.

Abstract: A compact millimeter-wave transmitter and receiver make use of interconnections within a chip-containing package for providing an integrated antenna. Due to shorter wavelength of millimeter-waves, these interconnections can be used as antennas for radiation of electromagnetic waves. A dielectric cover or lens is provided within the package to increase the antenna's directivity and to provide a mechanical shield for the chip.

Abstract: A low-cost and power-efficient communication system using digital frequency centering techniques suitable for millimeter-wave wide-bandwidth bands with mostly digital components. Significant circuitry in the frequency source can be switched-off, thus conserving power. With the use of non-coherent detection, power consumption can be further reduced as higher phase noise and lower frequency accuracy can be tolerated. In the first embodiment frequency centering is achieved with a multiple-state system which compares a frequency dependent unique state to a programmed or hardwired desired state. In an alternative embodiment this multiple-state system is implemented by means of a microcontroller through either software or hardware.

Abstract: A compact millimeter-wave transmitter and receiver make use of interconnections within a chip-containing package for providing an integrated antenna. Due to shorter wavelength of millimeter-waves, these interconnections can be used as antennas for radiation of electromagnetic waves. A dielectric cover or lens is provided within the package to increase the antenna's directivity and to provide a mechanical shield for the chip.

Abstract: In an embodiment, a termination for a transmission line (or high frequency circuit) includes a matching circuit which provides a matching impedance for the transmission line and an electrical connection between the two, e.g., a bond wire. The electrical connection has a reactance matrix, which, when combined with the impedance provided by the matching circuit, provides a resultant termination resistance.

Abstract: A balanced line switching apparatus that provides high isolation at an expense of a marginal increase of loss. Practical implementation can give as much as 40 dB isolation in a single stage.

Abstract: A dielectric transmission line bend structure includes an electrically conductive strip that forms a bend (e.g., a right angle bend). The inner edge of the bend includes a plurality of curved and/or straight line segments that result in the inner edge extending along a circuitous path in order to thereby reduce transmission line loss. A T-type junction includes a first or left side inner edge bending to the left and a second or right side inner edge bending to the right, with both inner edges including segments that result in greater inner edge lengths in order to increase current path lengths along the inner edges and thereby help reduce transmission line loss. A method of designing a transmission line bend structure includes the step of providing a preliminary bend structure design having an electrically conductive strip with at least one inner edge extending along a circuitous path between first and second inner edge end points on the strip.