Abstract: A circuit for generating a component of n-th order includes: six differential amplifiers (15A to 15F) having a pair of input terminals supplied with a common linear input signal and a constant level signal of a predetermined level, outputting a reversed or non-reversed signal to the linear input signal, and having a limiter function to limit the output signal to a predetermined maximum value and a minimum value; a constant level signal generation circuit for supplying the constant level signal to each of the six differential amplifiers; a current mirror circuit (14) for controlling current flowing in the differential amplifiers (15A to 15F); and addition resistors (16A, 16B) for adding the output current of the differential amplifiers (15A to 15F).

Abstract: A constant voltage generating circuit which uses a band gap reference circuit to produce a constant voltage and which is effective at reducing driving voltage and noise. The voltage generating circuit has a plurality of first bipolar transistors including n first bipolar transistors, each having an emitter area. The voltage generating circuit also includes a plurality of second bipolar transistors including n second bipolar transistors. Each of the n second bipolar transistors has an associated emitter area greater than the emitter area of each of the plurality of the first bipolar transistors. The constant voltage generating circuit produces a constant output voltage that is independent of temperature and the number of first and second transistors.

Abstract: A band-gap circuit is constituted by comprising a feedback control amplifier 31 and MOS transistors 32 and 35, having two transistors 33 and 34 of which emitter area is different, comprising resistors R1, R2 and Rp between a base and an emitter of the transistor 33 of which emitter area is smaller, having the resistor Rp between the base and a collector and comprising the resistors R1 and R2 between the base and emitter of the transistor 34 of which emitter area is larger. It is possible to provide the band-gap circuit operable at a low supply voltage and having high PSRR, low noise and few variations.

Abstract: To reduce a stop time of transportation of wafers which occurs when one stepper handles many kinds of products, before exposure of semiconductor wafers of a first cassette port 7a is completed, a process recipe for semiconductor wafers of a second cassette port 7b is obtained from a host computer 2, the progress of the exposure of the semiconductor wafers of the first cassette port 7a is detected via a sequencer 5, it is determined, based on the obtained process recipe, whether or not the semiconductor wafers of the second cassette port 7b can be transported to an exposure stage following the last semiconductor wafer of the first cassette port 7a, and a stepper 1 is caused to perform exposure in accordance with the determination result and the progress detection result.

Abstract: A high-speed current switch circuit of this invention has an n-type MOS transistor Q11 which switches and outputs a current, and a control circuit 11 which performs switching control of the MOS transistor Q11. In the control circuit 11, a source follower is formed by an N-type MOS transistor Q12 and a constant current source I2 which is a load on this transistor. A switch SW11 is connected to the MOS transistor Q12 to perform switching control of a current flowing through the MOS transistor Q12. The control circuit 11 includes a switch SW12 capable of grounding the gate of the MOS transistor 11. The source of the MOS transistor Q12 is connected to the gate of the MOS transistor Q11. Thus, even if a large current is caused to flow through the output transistor, the output transistor can be made to operate for switching at a high speed.

Abstract: A communication apparatus is provided which employs two oscillators to generate a transmission signal and a reception signal, and prevents harmful spurious components from being produced. As shown in FIGS. 9A and 9B, the oscillation frequency fVCO2 of a VCO 2 is given by fVCO2=N×(2×fDD), where fDD is the difference between the transmit frequency fT and receive frequency fR. A 3/(2×N) frequency multiplier outputs a signal with a frequency 3×fDD, and a divide-by-N circuit (2/(2×N) frequency multiplier) outputs a signal with a frequency 2×fDD. Thus the transmit intermediate frequency fTIF is given by fTIF=3×fDD, and the receive intermediate frequency fRIF is given by fRIF=2×fDD. The oscillation frequency fVCO1 of a VCO 1 is fCH. The transmit frequency fT is given by fT=fCH+fTIF=fCH+3×fDD. The circuit can prevent a transmission spurious problem to its own reception band.

Abstract: It is an object of the present invention to provide a constant voltage generating circuit which can reduce a driving voltage and noise. A resistor R1 is interposed between a pnp transistor PN11 and a base of a pnp transistor PN12. A resistor R2 is connected to a current source P11.

Abstract: The invention in the simplest form is a technique to provide for sharing of power and signal pins on a motor controller. The switching simply follows the magnetic switching detected by the Hall sensor as the motor magnet passes and uses a diode or resistor instead of a switch. The power transistors are respectively connected to a voltage regulator through a diode or resistor and there are no switches in the circuit. To avoid simultaneous switching, one embodiment is designed by turning “On” slowly and turn “Off” quickly. Slow “On” is accomplished by using a resistor/capacitor (RC) delay such that the gate drive ramps slowly. Fast “OFF” is obtained by discharging the gate capacitance with an N-CH transistor that bypasses the RC delay.

Abstract: To provide a mute circuit capable of reducing or eliminating noises generated in accordance with an offset voltage under a mute operation. The present invention comprises a summing amplifier, switch, and mute signal generating circuit.

Abstract: When a clock &phgr;1 is in high state, based on a digital signal, capacitive elements C11 to C1i are connected between a reference voltage Vr+ or Vr− and a sampling ground V1 to hold a charge corresponding to difference between the reference voltage and sampling ground V1 while capacitive elements C21 to C2i are connected between a reference voltage Vr+ or Vr− and a sampling ground V2 to hold a charge corresponding to difference between the reference voltage and sampling ground V2. When a clock &phgr;2 is in high state, the capacitive elements C11 to C1i and C21 to C2i are connected, in parallel with a feedback capacitive element Cfb, between an input terminal and output terminal of an operational amplifier 100. To obtain a D/A converter which operates at a lower supply voltage and produces output signals low in harmonic components and noise components.

Abstract: To provide a fully differential sampling circuit which reduces a sampling error to suppress the occurrence of a second harmonic component. The sampling error is resulted from voltage dependence of a capacitance of the capacitor formed on a semiconductor substrate. The present invention includes a first sampling capacitor 27, a second sampling capacitor 28, four switches 31, 32, 33′, and 34 for charging and discharging the first sampling capacitor 27, four switches 41, 42, 43′, and 44 for charging and discharging the second sampling capacitor 28, and a fully differential operational amplifier 20 including a first integral capacitor 25 and a second sampling capacitor 26. An upper layer electrode 28b and a lower layer electrode 28a of the second sampling capacitor 28 are opposite to the first sampling capacitor 27 in connecting direction (state).

Abstract: In an electronic circuit being provided with a plurality of circuit elements and performing a specified function, a plurality of specific circuit elements related to a circuit performing the specified function out of the plurality of circuit elements are composed of circuit elements changing their element parameters according to values indicated by control signals. The electronic circuit is provided with a plurality of holding circuits for holding a plurality of control signals to be given to the plurality of specific circuit elements. The values of the plurality of control signals which these holding circuits hold are changed by external or internal apparatuses according to a probabilistic searching technique (for example genetic algorithms or simulated annealing algorithms) so that the function of the electronic circuit satisfies designated specifications.

Abstract: A direct conversion receiving unit includes an oscillation circuit (50) whose oscillation frequency fvco is (N/(N+1))×fR, where fR is a receiving frequency. The output of the oscillation circuit (50) is divided into two parts, one of which is converted to the frequency of (1/(N+1))×fR by a divide-by-N circuit (52). Mixing the two frequencies (1/(N+1))×fR and fvco=(N/(N+1))×fR generates the frequency fR, which is supplied to conversion mixers (38 and 44) as a local input. The receiving unit requires only one oscillation circuit, and excludes all the circuits that handle a frequency higher than fR, enabling a small size and low current consumption configuration.

Abstract: When a clock &phgr;1 is in high state, based on a digital signal, capacitive elements C11 to C1i are connected between a reference voltage Vr+ or Vr− and a sampling ground V1 to hold a charge corresponding to difference between the reference voltage and sampling ground V1 while capacitive elements C21 to C2i are connected between a reference voltage Vr+ or Vr− and a sampling ground V2 to hold a charge corresponding to difference between the reference voltage and sampling ground V2. When a clock &phgr;2 is in high state, the capacitive elements C11 to C1i and C21 to C2i are connected, in parallel with a feedback capacitive element Cfb, between an input terminal and output terminal of an operational amplifier 100.

Abstract: This temperature-compensated crystal oscillator includes: a temperature sensor 11; an analog type temperature compensating section 12; a digital type temperature compensating section 13; an adder circuit 14; and a voltage controlled crystal oscillating circuit 3. The analog type temperature compensating section 12 and the digital type temperature compensating section 13 each generate temperature compensation voltages based on an input voltage corresponding to the temperature detected by the temperature sensor 11. Both of these temperature compensation voltages are added to each other by the adder circuit 14 and the resultant added voltage is applied to a voltage control terminal of the voltage-controlled crystal oscillating circuit 3. Thereby, an oscillation frequency of the voltage-controlled crystal oscillating circuit 3 is stabilized, resulting in realization of the temperature compensation of a crystal resonator 4.

Abstract: A high quality thermal oxide film is provided. For the purpose of the film, a cooling step is conducted after replacing an atmosphere in the diffusion furnace (1) with a high purity gas mixture of nitrogen N2 99% and oxygen O2 1% after an oxidizing and an annealing steps. Then, a pump (DP) is turned on to evacuate a load-lock chamber (6), which is then filled with nitrogen N2. Then, while feeding a gas mixture of nitrogen N2 99% and oxygen O2 1% into the diffusion furnace (1), a wafer boat (3) is transferred from the diffusion furnace (1) to the load-lock chamber (6) (Removing step). Thus, the cooling and the removing steps are conducted under an atmosphere gas of a high purity mixture of nitrogen and a small amount of high purity oxygen free from impurities in the air. Only high purity oxygen is, therefore, introduced in an interface between a silicon substrate and an oxide film, so that a high quality thermal oxide film can be provided.

Abstract: An approximate third-order function generator includes first, second, and third amplifiers, each receiving a common input signal and different fixed level signals. The three fixed level signals received respectively by the amplifiers sequentially increase in level. Each amplifier has an input-output characteristic whereby a non-inverted or inverted output signal is provided based on the common input signal and the fixed level signal. The fourth amplifier receives the same fixed level signal as the second amplifier and has an input-output characteristic in which a non-inverted or inverted output signal is provided based on the common input signal and the fixed level signal. The outputs of the first, third and fourth amplifiers have the same polarity, while that of the second amplifier is inverted. The output signals from the first, second, third and fourth amplifiers are added to generate a third-order function component free from the first-order component.

Abstract: The subject of the present invention is to keep the wiring resistance low and reduce the variation of the wiring resistance in one identical lot in semiconductor devices of a multi level interconnect structure in which at least the lower wiring layer is an aluminum wiring layer. Contact holes (31, 51) are formed in dielectric interlayers (3, 5) of upper and lower wiring layers (1, 2, 4) by dry etching. In the method of forming the contact holes of the invention, the dry etching was applied in two steps divisionally. The first step of etching is applied with supplying CF4, CHF3, Ar and N2 into an etching chamber. The second step of etching is conducted with supplying CF4, CHF3 and Ar into the etching gas chamber.

Abstract: A method for manufacturing a semiconductor device comprising a nonvolatile memory transistor of a stacked gate structure having a floating gate and a control gate, and a MOS transistor of a single gate structure, wherein the method comprises the steps of forming a first insulation film that becomes a gate oxide film of the transistors on a semiconductor substrate; forming a first conductive layer on the first insulation film; removing, from the first conductive layer, a region for separating a floating gate in a direction perpendicular to a direction in which the control gate is formed extendedly; forming a second insulation layer on the first conductive layer; forming a second conductive layer on the second insulation film; patterning the second conductive layer so as to form the control gate; and patterning the first conductive layer to form the stacked gate structure and the single gate structure.

Abstract: To shorten a process for manufacturing a semiconductor device comprising a silicide and a non-silicide diffusion layers and to form a stable and highly homogenous non-silicide diffusion layer, ions are implanted to form a source/drain diffusion layer and then the substrate is subjected to rapid thermal oxidation in a short time to activate the ions while forming a new oxide film. A thermal oxide film (6) consisting of the new oxide film including a protective oxide film (3) is etched to form an oxide film for preventing silicidation (8), a Ti film (9) is formed over the whole surface including the oxide film for preventing silicidation (8), the product is annealed for silicidation and the unreacted Ti film (9) is removed. Thus, a diffusion layer (4) as a non-silicide layer which is little silicided and a diffusion layer (5) whose surface is a silicide layer (10) are formed.