Abstract: To provide a fully differential sampling circuit which reduces a sampling error to suppress the occurrence of a second harmonic component. The sampling error is resulted from voltage dependence of a capacitance of the capacitor formed on a semiconductor substrate.

Abstract: An A/D converter (30) samples an analog signal synchronously with a sampling clock from a VCO (70). These sampled values are stored in a shift register (410). A code judging section (420) detects the positive/negative sign pattern (time-series code pattern) of the sampled values held in storage elements (S0 to S5) of the shift register (410) and stores the sampled values in predetermined register (431 to 434) according to the detected sign pattern. According to this, a calculating section (430) determines the phase difference between the analog signal and the sampling clock. The phase difference is fed to a VCO (70) through a D/A converter (50) and a loop filter (60).

Abstract: Silicon layers 2a, 2b comprised of different thicknesses are formed concurrently so as to be isolated from each other while a silicon oxide layer 1 serving as a foundation layer is controlled to be free from hollows by implanting ions only into a field silicon oxide layer 5a comprised of a thick film thickness among field silicon oxide layers 5a, 5b to be used for separating circuit elements, and thereby altering etching rates of the field silicon oxide layers 5a, 5b.

Abstract: A method for forming a semiconductor device having a capacitor, a resistor and a MOS transistor with characteristics conforming to design. To this end, a polysilicon film (4), a capacitor-dielectric/insulating film (5), a polysilicon film (6) are deposited, and an upper electrode (7) of the capacitor is formed from the polysilicon film (6), and edge portions (7a) of the upper electrode (7) are oxidized. On top of this, an inorganic anti-reflection coating film (9) and a CAP oxide film (10) are deposited and etched to form a mask pattern (12) for forming the capacitor and the resistor. On the other hand, a tungsten silicide film (13), an inorganic anti-reflection coating film (14) and a CAP oxide film (15) are deposited and etched to form a mask pattern (17) for forming a gate electrode. The polysilicon film (4) is etched by using the mask patterns (12) and (17), leaving behind the tungsten silicide film (13) beneath the mask pattern 17.

Abstract: On a silicon substrate 1 is provided a silicon oxide film 2, on which a polycrystalline silicon film 3 is formed by a low pressure CVD method at a monosilane partial pressure of no more than 10 Pa and a film formation temperature of no lower than 600° C. The polycrystalline silicon film is doped with an impurity such as phosphorus in a concentration of 1×1020 atoms/cm3 to 1×1021 atoms/cm3 to form a phosphosilicate glass film 6, and after removing it, the polycrystalline silicon film is thermally oxidized in an oxidative atmosphere to form a dielectric film 5 on the surface. A polycrystalline silicon film 4 is formed on the dielectric film 5, which is treated as the oriented polycrystalline silicon film 3a to form an oriented polycrystalline silicon film 4a. The oriented polycrystalline silicon film 4a as an upper electrode and the oriented polycrystalline silicon film 3a as a lower electrode are wired to obtain a semiconductor device having a capacitor.

Abstract: An automatic dynamic range control circuit is provided with a fixed-gain first circuit means and a variable-gain second circuit means having substantially the same propagation delay as the first circuit means. The automatic dynamic range control circuit holds the peak value of an input signal, selects the first circuit means when this peak value is smaller than a reference signal level, and selects the second circuit means when the peak value exceeds this reference signal level. When the held peak value is smaller than the reference signal level, the second circuit means is operated at the same gain relative to an input signal as the first circuit means by having its gain set by the reference signal. When the held peak value exceeds the reference signal, the gain of the second circuit means is limited by this held peak value and its output level is kept at or below a prescribed level.

Abstract: On a silicon substrate 1 is provided a silicon oxide film 2, on which a polycrystalline silicon film 3 is formed by a low pressure CVD method at a monosilane partial pressure of no more than 10 Pa and a film formation temperature of no lower than 600.degree. C. The polycrystalline silicon film is doped with an impurity such as phosphorus in a concentration of 1.times.10.sup.20 atoms/cm.sup.3 to 1.times.10.sup.21 atoms/cm.sup.3 to form a phosphosilicate glass film 6, and after removing it, the polycrystalline silicon film is thermally oxidized in an oxidative atmosphere to form a dielectric film 5 on the surface. A polycrystalline silicon film 4 is formed on the dielectric film 5, which is treated as the oriented polycrystalline silicon film 3a to form an oriented polycrystalline silicon film 4a. The oriented polycrystalline silicon film 4a as an upper electrode and the oriented polycrystalline silicon film 3a as a lower electrode are wired to obtain a semiconductor device having a capacitor.

Abstract: A D/A converter for converting a given digital signal into an analog signal includes a plurality of capacitors (C1, C2 . . . , Ci) for storing an electric charge corresponding to a predetermined reference voltage (Vr+or Vr-). The reference voltage is selected depending on the digital signal during a period when a clock .phi.1 is at a high level. A switch selection (SUG1-SUGi, SB) is used to connect each of the plurality of capacitors between an input terminal and an output terminal of an operational amplifier 100 during a period when a clock +2 is at a high level.

Abstract: A clock combining circuit includes a FIFO circuit, a signal combining circuit and a signal selecting circuit. The FIFO circuit accepts, for example, a positive-edge playback signal RDATA0 that has as data the positive edge of a playback signal obtained from recording domains formed in a recording medium, RDATA0 being synchronized with a positive-edge clock signal RCLK0. The FIFO circuit also accepts a negative-edge playback signal RDATA1 that has as data the negative edge of the playback signal, RDATA1 being synchronized with a negative-edge clock signal RCLK1. The FIFO circuit causes RDATA0 and RDATA1 to be synchronized with RCLK0 so as to output a delayed positive-edge playback signal RDATA0D and a delayed negative-edge playback signal RDATA1D. The delayed negative-edge playback signal is delayed by -KT to +LT, where K and L are integers and T is the clock period. The signal combining circuit combines the delayed positive-edge and negative-edge playback signals, and outputs (K+L+1) combined signals.

Abstract: An information playback apparatus includes a clock combining circuit having a FIFO circuit, a signal combining circuit and a signal selecting circuit. The FIFO circuit accepts, for example, a positive-edge playback signal RDATA0 that has as data the positive edge of a playback signal obtained from recording domains formed in a recording medium, RDATA0 being synchronized with a positive-edge clock signal RCLK0. The FIFO circuit also accepts a negative-edge playback signal RDATA1 that has as data the negative edge of the playback signal, RDATA1 being synchronized with a negative-edge clock signal RCLK1. The FIFO circuit causes RDATA0 and RDATA1 to be synchronized with RCLK0 so as to output a delayed positive-edge playback signal RDATA0D and a delayed negative-edge playback signal RDATA1D. The delayed negative-edge playback signal is delayed by -KT to +LT, where K and L are integers and T is the clock period.

Abstract: A digital filter is provided for achieving substantial attenuation of aliasing or imaging bands of a signal to be filtered. The digital filter employs a comb filter technique, wherein the comb filter can perform decimation or interpolation, depending upon its application. The comb filter is a multi-stage element, having more than one stage, and having an overall word length, W.sub.L, optimally reduced. The total number of terms within the cumulative set of stages is also optimally reduced. The comb decimation or interpolation filter architecture is therefore of minimum size if employed in hardware, or utilizes minimal operations if employed in software. A filter element within the comb decimation or interpolation filter includes a z-transform C.sub.K (Z) term. The filter element can be reduced to a simple z-transform 1+z.sup.-1 term if the stage of interest includes a decimate-by-two or interpolate-by-two rate change switch.

Abstract: A D/A switched capacitor circuit, employed as part of a delta-sigma modulator, is provided. The modulator forms part of an A/D converter system, and the switched capacitor circuit is controlled by careful selection of clock phases. The clock phases, or more specifically four clock phases, are provided to ground both plates of switched capacitors within the D/A circuit subsequent to their discharge upon the integrator and prior to the next sampling period. Full discharge of shared capacitors to a ground voltage substantially eliminates any data dependent loading of integrator offset voltages upon the reference voltage supplies. Substantial reduction or elimination of data-dependent values prevents ac modulation of the referenced voltage supply and the imputed noise associated therewith.

Abstract: A method of fabricating a semiconductor device having a semiconductor substrate, a MOS transistor formed on one surface of the semiconductor substrate, and a capacitor is disclosed. The MOS has a gate electrode with a polycrystalline silicon layer and a metal silicide layer. The capacitor includes a first polycrystalline silicon layer which forms a lower electrode layer, an insulating interlayer, and a second polycrystalline silicon layer which forms an upper electrode, the first and second polycrystalline silicon layers sandwiching the insulating interlayer.

Abstract: An analog arithmetic circuit for executing multiplications, divisions, compressions, expansions and combinations thereof. The arithmetic circuit is provided with a .DELTA..SIGMA. modulator comprising an A/D converter and a first D/A converter, a second D/A converter for receiving the output from the .DELTA..SIGMA. modulator, and a low-pass filter which receives the output of the second D/A converter and outputs the result of an arithmetic operation. The arithmetic circuit can be fabricated in the form of a MOS LSI because it does not use a precise triangle waveform generator for pulse width modulation.