Abstract: The digital television system that has a zoom module. When the digital television system is in a zoom mode, the zoom module receives a full frame, and displays the zoom frame that includes only a portion of the full frame. The zoom module determines a relationship between the zoom frame and the full frame. The zoom module also identifies an object within a zoom frame, and a motion vector of the object with respect to a background of the zoom frame. As the object moves within the zoom frame, the zoom module adjusts relationship between the zoom frame and the full frame so that the object remains within the zoom frame.

Abstract: A method and apparatus for producing a fragment descriptor for use in oversampling anti-aliasing includes processing that begins by generating a single representative color value for a plurality of subpixels of a pixel. The processing then continues by generating a single representative Z value for the pixel. The processing continues by generating masking information for the pixel, wherein the masking information indicates, for a given object-element being rendered, coverage of the pixel by the object-element. The processing continues by packing the single representative color value, the single representative Z value, and the masking information into a fragment descriptor. The processing continues by transporting the fragment descriptor to a custom memory. When the custom memory receives the fragment descriptor it unpacks it to recapture the single representative color value, the single representative Z value and the masking information.

Abstract: A method and a computer for performance of the method. While executing a program on a computer, profileable events occurring in the instruction pipeline are detected. The instruction pipeline is directed to record profile information describing the profileable events essentially concurrently with the occurrence of the profileable events. The detecting and recording occur under control of hardware of the computer without software intervention.

Abstract: In a specific embodiment of the present invention, a graphics device generates digital output data in response to a known input data. The resulting digital output data has an expected circular redundancy check (CRC) value. The generated digital output data is provided to a digital graphics output port associated with the graphics controller, which is thereby transmitted to a test apparatus over a digital graphics cable. The test apparatus performs an analysis on the received digital graphics data. The analysis results are transmitted back to the graphics device over a serial link of the digital display cable. The graphics device receives the transmitted analysis data, which is subsequently used to determine if the graphics device is operating properly. This determination may be made the graphics device, or by a host system for further analysis.

Abstract: A method for processing video image data including a plurality of different image data types begins by providing tasks to be performed on each different image data type. The image data is divided into a plurality of groups based on the image data type. A set of arithmetic operations required to accomplish the tasks provided for the corresponding image data type is determined. Each arithmetic operation is assigned to one of a plurality of commonly used arithmetic units which performs the arithmetic operation, whereby each image data type is transformed in accordance with the corresponding provided tasks. The transformed image data of each group is combined, completing the processing.

Abstract: A ring oscillator produces an in-phase and quadrature phase radio frequency signal. A first mixer mixes the in-phase signal with a received signal. A second mixer mixes the quadrature phase signal with the received signal. A combiner, operatively coupled to the first and second mixers, produces an image cancelled signal.

Abstract: A computer having an instruction pipeline and profile circuitry. The profile circuitry detects and records, without compiler assistance for execution profiling, profile information describing a sequence of events occurring in the instruction pipeline. The sequence includes every event occurring during a profiled execution interval that matches time-independent selection criteria of events to be profiled. The recording continues until a predetermined stop condition is reached. The profile circuitry detects the occurrence of a predetermined condition, after a non-profiled interval of execution, and then commences the profiled execution interval.

Abstract: A method and apparatus for controlling display of content signals begins by receiving a content signal that includes video content and at least one associated content control indicator. The content signal may also include audio content associated with the video content. The processing continues by comparing the at least one associated content control indicator (e.g., a rating of mature subject matter of the content signal) with at least one content control setting (e.g., a parental setting based on allowable viewing of rated content signals). When the associated content indicator compares unfavorably to the content control setting, a video graphics processor scrambles the at least a portion of the video content. The scrambled video content is then provided to a video rendering device for subsequent display.

Abstract: A method for deinterlacing interlaced video using a graphics processor includes receiving at least one instruction for a 2D/3D engine to facilitate creation of an adaptively deinterlaced frame image from at least a first interlaced field. The method also includes performing, by the 2D/3D engine, at least a portion of adaptive deinterlacing based on at least the first interlaced field, in response to the at least one instruction to produce at least a portion of the adaptively deinterlaced frame image. Once the information is deinterlaced, the method includes retrieving, by a graphics processor display engine, the stored adaptively deinterlaced frame image generated by the 2D/3D engine, for display on one or more display devices. The method also includes issuing 2D/3D instructions to the 2D/3D engine to carry out deinterlacing of lines of video data from interlaced fields. This may be done, for example, by another processing device, such as a host CPU, or any other suitable processing device.

Abstract: A method and apparatus for processing graphics primitives that includes a trivial discard guard band. Such a trivial discard guard band is used for comparison operations with the vertices of graphics primitives to determine whether the graphics primitives can be trivially discarded such that no further processing of the primitives is performed. The trivial discard guard band may be based on the specific dimensions of primitives such as one-half of the width of the line primitives or the radial dimension of point primitives such that the rasterization area of such primitives is taken into account when trivial discard decisions are performed.

Abstract: Multi-thread video data processing for use in a computer video display system. The parameters of vertex data are grouped into a plurality of groups. The computation needs of each group are broken down into several arithmetic operations to be performed by corresponding arithmetic units. The units concurrently process the vertex data.

Abstract: The computer system operates a plurality of display devices 100 and 102. Such a computer system has at least a first video adapter 203 with a first video BIOS and a second video adapter 207 with a second video BIOS. A system BIOS identifies one of the first and second video adapters 203, 207 as a primary video adapter and the other of the first and second video adapters 203, 207 as a secondary video adapter. During POST, the system BIOS stores the first video BIOS in a first memory area 210 in a system memory 212 of the computer. The system BIOS or Video BIOS then copies the first video BIOS to a second memory area 214 in the system memory 212 when the first video adapter 203 is the secondary video adapter. The system BIOS POSTs the second video BIOS when the second video adapter 207 is the primary video adapter, and stores the second video BIOS in the first memory area 210. This then causes the first video BIOS in the first memory area 210 to be overwritten by the second video BIOS.

Abstract: An instruction processor to execute two instruction sets. Instructions are stored in different virtual memory pages of a single address space, and are coded for computers of two different instruction sets, and use of two different calling conventions. The instruction processor interprets instructions under, alternately, the first or second instruction set as directed by a first flag stored in table entries corresponding to memory pages for the instructions. The processor recognizes when program execution has transferred from a page of instructions using the first data storage convention to a page of instructions using the second data storage convention, as indicated by a second flag stored in the table entries, and then adjusts a data storage content of the computer from the first storage convention to the second data storage convention. A history record provides a record of a classification of a recently-executed instruction.

Abstract: A dynamic component to input signal mapping system is disclosed that receives different types of input signals applied to a number of components and provides resultant output signals. The system includes input ports receiving the input signals, output ports providing the output signals, and a number of components processing the input signals, each of the components having at least one input and one output. The system includes a test signal source coupled to the components. Additionally, a signal analyzer coupled to an output of components analyzes response signals output from the components in response to test signals. The system is operative to map at least one component to receive at least one input signal based on the analyzed response. The system allows components on a semiconductor chip to be dynamically reconfigured for optimal processing of different types of signals, such as video and audio signals.

Abstract: A method and apparatus for processing non-planar video graphics primitives is presented. Vertex parameters corresponding to vertices of a video graphics primitive are received, where the video graphics primitive is a non-planar, or higher-order, video graphics primitive. A cubic Bezier control mesh is calculated using the vertex parameters provided for the non-planar video graphics primitive. Two techniques for calculating control points included in the cubic Bezier control mesh along the edges of the non-planar video graphics primitive are described. The central control point is determined based on the average of a set of reflected vertices, where each of the reflected vertices is a vertex of the non-planar video graphics primitive reflected through a line defined by a pair of control points corresponding to the vertex.

Abstract: A computer. An instruction pipeline and memory access unit execute instructions in a logical address space of a memory of the computer. An address translation circuit translates address references generated by the program from the program's logical address space to the computer's physical address space. Profile circuitry is cooperatively interconnected with the instruction pipeline and configured to detect, without compiler assistance for execution profiling, occurrence of profilable events occurring in the instruction pipeline, and is cooperatively interconnected with the memory access unit to record profile information describing physical memory addresses referenced during an execution interval of the program.

Abstract: A computer has a multi-stage execution pipeline and an instruction decoder.

Abstract: A copy protection (CP) key used by a sending source, such as a POD, to encrypt content such as audio and/or video information is derived by a first key generator associated with a first processor and is locally encrypted by the first processor using a locally generated bus encryption key to produce a bus encrypted CP key that is sent over a local unsecure bus to a second processor, such as a graphics processor. The second processor decrypts the bus encrypted copy key using a decryption engine to obtain the CP key. The second processor receives the encrypted content and in one embodiment, also uses the same decryption engine to decrypt the encrypted content. The first and second processors locally exchange public keys to each locally derive a bus encryption key used to encrypt the CP key before it is sent over the unsecure bus and decrypt the encrypted CP key after it is sent over the bus.

Abstract: A reference signal input of a delay locked loop is connected to receive a reference clock. The delay locked loop provides a drive clock that drives a clock distribution tree. One of the endpoints of the clock distribution tree is connected to a feedback reference of the delay locked loop. By using one the endpoints as a feedback loop to the delay locked loop the signal received at components attached to the endpoints of the distribution tree can be synchronized to the reference input received at the delay locked loop.

Abstract: A method and apparatus for constructing an executable program, such as drivers in memory, obtains system configuration parameters and dynamically constructs driver code bundles from a set of code modules obtained from a library, based on the actual system configuration parameters. The set of code modules includes code modules associated with a plurality of system configuration parameters. One example of the system configuration parameter include static system configuration parameters such as in the case of a computer, a CPU type, clock speed and system memory size. Other actual system configuration parameters include dynamic configuration parameters which can be changed by the user. One example of a dynamic configuration parameter may be, for example, pixel depth and display screen resolution. After obtaining optimal system configuration depending upon a system's setting or configurations, dedicated code modules are used and stored in system memory or other suitable memory.