Abstract: A display FIFO memory management system and method includes a programmable FIFO emulator for emulating a drain and fill time of the display FIFO memory to automatically predict a number of register entries remaining in the display FIFO memory at each predefined clock cycle. A programmable timer/counter has programmable precision to accommodate varying bandwidths of display screen display modes and is used to determine the number of entries remaining so that the emulator can accommodate varying screen display modes. A FIFO controller controls the timing of fetching display data from memory to fill the display FIFO memory based on the prediction of the number of remaining register entries in the display FIFO by the programmable emulator.

Abstract: An adapter (e.g., connector, dongle) is used to connect a component video television, such as an SDTV or HDTV, to a video providing unit, such as a computer or any other suitable video providing unit, that includes a plurality of video input pins, a plurality of video output pins, a plurality of control pins and a circuit. The circuit is operative to identify to a video providing unit through the control pins, that the component video input television is not of a display type that the video providing unit expects.

Abstract: A method and apparatus for frame synchronization in a display circuit is achieved by first measuring a difference between a first frame period and a second frame period. When the difference exceeds a threshold, the first frame period is adjusted by replacing the clock corresponding to the first frame period with one of a slow frame rate and a fast frame rate. The slow and fast frame rates closely approximate an ideal frame rate that would synchronize the two frame periods. By switching between the slow and fast frame rates, the average frame rate approaches the ideal frame rate over time, and the two frame periods are effectively synchronized.

Abstract: A method and apparatus for detecting copy protection included in an input video signal is described. Two types of copy protection are particularly addressed, including techniques that imbed copy protection pulses and copy protection phase flips in the video signal. A method for preserving copy protection is also presented, where the input video signal is first examined to determine if copy protection has been included in the input video signal. The input video signal then converted to component video data, which removes any copy protection present. An output video signal is then generated from the component video data, and when it was determined that the input video signal includes copy protection, the copy protection is recreated in the output video signal.

Abstract: In one embodiment of the present invention, an application responds to a low power operation request based upon its current state. In another mode, the application responds based upon its own current state and the state of a second application. Examples of such low power application requests include a suspend operation request issued by an operating system. Examples of such applications include multi-media applications.

Abstract: A method and apparatus for adjusting the amplitude and DC bias of a video signal is presented, which may be performed in preparation for analog-to-digital conversion. This is accomplished by first converting a received voltage mode video signal to a current mode video signal. Similarly, a voltage mode bias control signal is converted to a current mode bias control signal. The amplitude of the current mode video signal is then adjusted to produce an amplitude adjusted video signal. Similarly, the amplitude of the current mode bias signal is adjusted to produce an amplitude adjusted bias control signal. The current mode amplitude adjusted signals are then combined to produce a biased adjusted current mode video signal. The biased adjusted current mode video signal is then converted back to a voltage mode signal, which may be provided to an analog-to-digital converter for conversion.

Abstract: A multiple device frame synchronization method and apparatus utilizes events completion signaling between multiple devices, such as multiple graphics processors. The signaling serves as a stall command for stalling graphics data rendering commands in a command FIFO of the rendering engine of a graphics processor in response to a rendering complete signal, or other event signal generated by the other graphics processor. Accordingly, the processor that, for example, completes a current frame relay is stalled until the other processor has completed its rendering function for a particular odd line, even line, entire frame or partial frame as desired.

Abstract: A method and apparatus for ensuring data coherency in a processing system that includes shared memory is presented. This is accomplished by including a hierarchical validity database within the core logic that interconnects the various memory clients to the memory structure. The hierarchical validity database stores a number of hierarchical levels, where each level pertains to different sized portions of the memory. Validity of a portion, or block, within the memory can be determined by referencing the hierarchical validity database.

Abstract: A cache controller (210) includes a streaming memory attribute. The cache controller (210) is coupled to provide data from a cache line within a cache (228) to a memory (124) when both (a) the cache line is full and (b) the streaming memory attribute is set.

Abstract: A method and apparatus for determining a rear most Z value for a pixel block is presented, where the pixel block is a portion of the image data for a frame as stored in a frame buffer. The frame buffer is stored in a DRAM memory structure that is included on an integrated circuit along with a render backend block that blends received fragments from a three-dimensional (3D) video graphics pipeline with the image data stored in the frame buffer. The 3D video graphics pipeline is located on a video graphics processing integrated circuit separate from the integrated circuit storing the frame buffer and render backend block. The integrated circuit storing the frame buffer includes a value determination block that determines the rear most Z value. The value determination block includes a data serialization block that serializes the bits corresponding to the Z values for the pixels included in the pixel block to produce a plurality of corresponding serial bit streams.

Abstract: A method and apparatus for reducing latency in pipelined circuits that process dependent operations is presented. In order to reduce latency for dependent operations, a pre-accumulation register is included in an operation pipeline between a first operation unit and a second operation unit. The pre-accumulation register stores a first result produced by the first operation unit during a first operation. When the first operation unit completes a second operation to produce a second result, the first result stored in the pre-accumulation register is presented to the second operation unit along with the second result as input operands.

Abstract: In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.

Abstract: A method and apparatus for avoiding latency in a processing system that includes a memory for storing intermediate results is presented. The processing system stores results produced by an operation unit in memory, where the results may be used by subsequent dependent operations. In order to avoid the latency of the memory, the output for the operation unit may be routed directly back into the operation unit as a subsequent operand. Furthermore, one or more memory bypass registers are included such that the results produced by the operation unit during recent operations that have not yet satisfied the latency requirements of the memory are also available. A first memory bypass register may thus provide the result of an operation that completed one cycle earlier, a second memory bypass register may provide the result of an operation that completed two cycles earlier, etc.

Abstract: A method and apparatus for processing portions of primitives that are being rendered is presented. Primitives that are received are divided into portions that correspond to pixel blocks of the frame. The frame includes a plurality of pixel blocks where each of the pixel blocks includes a plurality of pixels that are included in the frame. Thus, the pixel blocks divide the frame into a number of smaller blocks. A representative Z value for each portion of the primitive is determined, and the representative Z value for the portion of the primitive is compared with a representative buffered Z, which may be the representative buffer Z value for the pixel block to which the portion corresponds. If the representative Z value for the portion compares favorably with the representative buffered Z value such that the portion is determined to lie completely behind the information currently stored for that pixel block, the portion is discarded.

Abstract: A method and apparatus compresses digital information based on an interpolation function such as used by a graphic engine scaler. Luma error information is determined based on the interpolation function and original luma data. A luma error quantizer quantizes the luma error information to determine a quantized error value on a per pixel basis. The quantized luma error value is compressed as part of compressed video information. In addition, chroma information is also compressed and combined with the compressed luma and compressed error information. The video compression method and apparatus stores compressed digital luma information, compressed digital chroma information, and compressed quantized error information (values) as the compressed video information on a per frame basis.

Abstract: The video decoding apparatus and method includes providing a storage pointer command over a bus for a video decoder, wherein the storage pointer command contains index data associated with compressed video data. The index data represents, for example, a buffer storage location in a buffer that stores both decoded video being displayed and simultaneously uses another portion of the same buffer for decoding, such that the index data represents the storage location where corresponding decoded data is finally stored before display. The index data is compared with a current index or pointer associated with a current display line of a display engine. The apparatus and method includes stalling storage of compressed or uncompressed video data based on the comparison.

Abstract: An address access control system dynamically forms a plurality of address ranges in a predefined unified address structure during operation of a computer system. A plurality of memory clients is operatively connected to the unified address structure. A plurality of capabilities is also provided with respect to memory clients accessing address ranges. A memory controller is operatively connected to the plurality of memory clients and to the unified address structure. The memory controller dynamically structures an association of a respective range of the plurality of ranges with at least one respective capability of a plurality of capabilities for at least one memory client of the plurality of memory clients.

Abstract: A computer system has at least one processor and at least one queue for storing instructions for execution by the processor. The processor is capable of being clocked at a plurality of rates. A number of instructions in the queue is measured. The optimum clock rate is selected based on in part the determined number of queued instructions.

Abstract: A method and apparatus for storing multimedia data for use in a digital VCR includes processing that begins by maintaining a first link list of a plurality of memory sections, where the first link list links the plurality of memory sections as a circular buffer. The processing then continues by receiving a stream of multimedia data. The processing then continues by storing the stream of multimedia data in at least some of the memory sections of the plurality of memory sections. The processing then continues by receiving a request for independent storage of a selected portion of the stream of multimedia data, e.g., the user desires to have a permanent copy of a particular program. The processing further continues by generating a second link list for a set of memory sections of the at least some of the memory sections. The set of memory sections stores the selected portion of the stream of multimedia data.

Abstract: In a specific embodiment of the present invention RGB video data is converted to a YUV video data representation. The YUV video data is compressed and transmitted over a data bus to a memory device. Also transmitted is a compression indicator. The memory device buffers arid decompresses the compressed data. The decompressed data is converted back into uncompressed RGB video, and stored in a memory array. During a read cycle, the RGB data is converted into YUV video data, and compressed at the memory before being transmitted to the graphics processor along with a compression indicator. The graphics processor decompresses the data and provides it to the requesting client.