Abstract: A method for configuring a multi-port digital subscriber line (DSL) modem, the method begins by utilizing frequency bands of a single DSL channel to support a data communication when loop length of the single DSL channel and data rate of the data communication are favorable. The method continues by utilizing some of the frequency bands of the single DSL channel and frequency bands of at least one other DSL channel to support the data communication when the loop length of the single DSL channel is unfavorable or the data rate of the data communication is unfavorable.

Abstract: A linearized oscillation synthesizer includes a phase and frequency detection module, charge pump circuit, low pass filter, voltage control oscillator, and a feedback module. The phase and frequency detection module is operably coupled to produce a charge-up signal, a charge-down signal, and an off signal based on phase and/or frequency differences between a reference oscillation and a feedback oscillation. The reference oscillation is generated by a clock source such as a crystal oscillator while the divider module generates the feedback oscillation by dividing the output oscillation by a divider value. The charge pump circuit produces a positive current in response to the charge-up signal, a negative current in response to the charge-down signal and also produces a non-zero offset current. The non-zero offset current shifts the steady state operating condition, and other operating conditions, of the charge pump into a linear region of charge pump performance curve.

Abstract: A divider module for use in an oscillation synthesizer includes a plurality of flip-flops and a logic circuit. The plurality of flip-flops is interoperably coupled to produce a divider value based on a control signal. The logic circuit is operably coupled to produce the control signal based on divider select signals. Each of the plurality of flip-flops includes a first differential latch module, a second differential latch module. The first differential latch module is operably coupled to produce a differential latched signal based on a differential flip-flop input signal. The second differential latch module is operably coupled to produce a differential flip-flop output based on the differential latched signal. Each of the first and second differential latch modules includes a sample transistor section, a hold transistor section, a first gating circuit, and a second gating circuit.

Abstract: A radio frequency (RF) integrated circuit (IC) includes a local oscillation module, analog radio receiver, analog radio transmitter, digital receiver module, digital transmitter module, and digital optimization module. The local oscillation module is operably coupled to produce at least one local oscillation. The analog radio receiver is operably coupled to directly convert inbound RF signals into inbound low intermediate frequency signals based on the local oscillation. The digital receiver module is operably coupled to process the inbound low IF signals in accordance with one of a plurality of radio transceiving standards to produce inbound data. The digital transmitter is operably coupled to produce an outbound low intermediate frequency signal by processing outbound data in accordance with the one of the plurality of radio transceiving standards. The analog radio transmitter is operably coupled to directly convert the outbound low IF signals into outbound RF signals based on the local oscillation.

Abstract: An on-chip inductor may be fabricated by creating at least one dielectric layer, creating at least one conductive winding on the at least one dielectric layer and creating: (1) a P-well layer having a major surface parallel to a major surface of the dielectric layer, (2) field oxide layer having a major surface parallel to a major surface of the dielectric layer, (3) P-well and field oxide layer, or (4) a poly-silicon layer having a major surface parallel to a major surface of the dielectric layer.

Abstract: A method for determining a peak value of a radio frequency (RF) signal begins by receiving an RF signal. The method continues by high pass filtering the RF signal to produce a first input. The method continues by rectifying the first input signal with respect to a rectifying input to produce a rectified signal. The method continues by low pass filtering the rectified signal to produce the peak value.

Abstract: An integrated multimode radio includes a multimode receiver and a multimode transmitter. The multimode receiver includes a shared receiver front-end, a receiver multiplexor, and a plurality of receiver IF stages. The multimode transmitter includes a shared transmitter front-end, a transmitter multiplexor, and a plurality of transmitter IF stages.

Abstract: An unconditionally stable on-chip filter includes a filtering section and at least one negative resistance module. The filtering section is operably coupled to filter a signal and includes realizable integrated circuit passive components. The at least one negative resistance module is operably coupled to compensate for integrated circuit losses of the filtering section. The realizable integrated circuit passive components have values that are robust, in comparison to parasitic values, have minimal integrated circuit real estate, and provide realizable values for various integrated circuit manufacturing processes including CMOS technology.

Abstract: A packetized I/O link such as the HyperTransport protocol is adapted to transport memory coherency transactions over the link to support cache coherency in distributed shared memory systems. The I/O link protocol is adapted to include additional virtual channels that can carry command packets for coherency transactions over the link in a format that is acceptable to the I/O protocol. The coherency transactions support cache coherency between processing nodes interconnected by the link. Each processing node may include processing resources that themselves share memory, such as symmetrical multiprocessor configuration. In this case, coherency will have to be maintained both at the intranode level as well as the internode level. A remote line directory is maintained by each processing node so that it can track the state and location of all of the lines from its local memory that have been provided to other remote nodes.

Abstract: A differential linear fractional N-synthesizer includes a phase and frequency detection module, a linearized charge pump, a low pass filter, a voltage controlled oscillator, and a fractional N divider feedback. The phase and frequency detection module is operably coupled to produce a differential charge-up signal, a differential charge-down signal, or a differential off signal based on phase and/or frequency differences between a reference oscillation and a feedback oscillation. The feedback oscillation is generated by the fractional N divider feedback, which divides an output oscillation by a divider value to produce the feedback oscillation. The linearized charge pump includes a 1st current source, a 2nd current source and a modulation module. In response to the differential off signal, the modulation module produces a modulated differential off signal that causes the 1st and 2nd current sources to produce a zero current signal in an alternating fashion.

Abstract: An on-chip inductor and/or on-chip transformer includes at least one dielectric layer and at least one conductive winding on the at least one dielectric layer. The conductive winding has a substantially square geometry and has at least its exterior corners geometrically shaped to reduce impedance of the conductive winding at a particular operating frequency. Since the quality factor of an on-chip inductor is inversely proportional to the effective series impedance of an inductor at an operating frequency, by reducing the effective series impedance, the quality factor is increased.

Abstract: An RF antenna coupling structure includes a first transformer, a second transformer, and a transformer balun. The first transformer includes a primary winding and a secondary winding, wherein the primary winding of the first transformer is operably coupled to a power amplifier, and wherein the secondary winding of the first transformer has a desired output impedance corresponding to the operational needs of the power amplifier. The second transformer includes a primary winding and a secondary winding, wherein the primary winding of the second transformer is operably coupled to a low noise amplifier, and wherein the secondary winding of the second transformer has a desired output impedance corresponding to the needs of the low noise amplifier. The transformer balun includes a differential winding and a single-ended winding, wherein the differential winding is operably coupled to the secondary windings of the first and second transformers and the single-ended winding is operably coupled to an antenna.

Abstract: A method and apparatus for direct tuning of a component embedded within an integrated circuit includes processing that begins by providing a plurality of frequency dependent control input signals to an input of the integrated circuit. The processing continues for each of the plurality of frequency dependent control input signals by incrementally adjusting the power level of each frequency dependent controlled input signal until the signal strength of an output of the integrated circuit is at a desired signal strength level. The corresponding power level is recorded to produce an adjusted power level for the frequency dependent control input signal. The adjusted power level of each of the plurality of frequency dependent control input signals is plotted to produce a signal strength to frequency relationship. The processing continues by comparing the signal strength to frequency relationship with a desired signal strength to frequency relationship.

Abstract: A method for calibrating a filter begins with the filter filtering a first signal having a first frequency to produce a first filtered signal, wherein the first frequency is in a known pass region of the filter. The processing continues by measuring signal strength of the first filtered signal to produce a first measured signal strength. The processing continues with the filter filtering a second signal having a second frequency to produce a second filtered signal, wherein the second frequency is at a desired corner frequency of the filter. The processing continues by measuring signal strength of the second filtered signal to produce a second measured signal strength. The processing continues by comparing the first measured signal strength with the second measured signal strength to determine whether the filter has attenuated the second signal by a desired attenuation value with respect to the first signal.

Abstract: The present invention provides a method for tuning output drivers to an operating frequency based on settings used to tune other devices within the device such as a VCO. First the VCO within a PLL and clock circuit is tuned to the desired operating frequency. This operating frequency then corresponds to a discrete tuning setting. The discrete setting that causes the VCO to function at the operating frequency are then transferred to scaled amplifiers within output drivers. These drivers are then tuned to the operating frequency with these settings. This process eliminates the need to individually tune each output driver to function properly at the operating frequency.

Abstract: A digital demodulator that may be utilized in integrated radio receivers and/or integrated radios includes a mixing section, 1st and 2nd digital comb filters, phase locked loop module, and a data recovery module. The mixing section is operably coupled to produce a digital I signal and a digital Q signal from a digital intermediate frequency signal. The 1st comb filter filters the digital I signal while the 2nd comb filter filters the digital Q signal. The phase locked loop module produces a digital signal from the filtered I and filtered Q signals. The data recovery module interprets the digital signal to recapture a data stream.

Abstract: An on-chip impedance matching includes a transistor, an inductor, and a capacitive divider. The gate of the transistor is operably coupled to receive input signals; the source of the transistor is coupled to a first DC voltage potential; and the drain of the transistor is operably coupled to the inductor. The other end of the inductor is operably coupled to a second DC voltage potential. The capacitive divider includes matched capacitors that, in combination with the inductor, provide for substantially lossless on-chip impedance matching, where a tap of the capacitive divider provides an output of the on-chip impedance matching power amplifier. In addition, the capacitance of the capacitive divider and the inductance of the inductor are tuned to provide a tank circuit for the on-chip impedance matching power amplifier.

Abstract: A method for generating a modulo Gray-code representation of a non-power-of-two set of binary values begins by determining a desired Gray-code sequence length. The method then continues by determining a bus width, M, in bits, based on the desired Gray-code sequence length, to represent the generated Gray-code. The method then continues by determining a set of skipped binary values based on the desired Gray-code sequence length and the bus width to obtain the non-power-of-two set of binary values. The method then continues by representing the non-power-of-two set of binary values as a set of equivalent Gray-code values.

Abstract: A power amplifier includes an input transistor, an input bias circuit, an output transistor, and a power down circuit. The input transistor includes a gate, a drain, and a source, wherein the source of the input transistor is coupled to a supply voltage return and the gate of the input transistor is operably coupled to receive an outbound radio frequency (RF) signal. The input bias circuit is operably coupled to provide an enabling bias voltage to the gate of the input transistor during transmit mode and to provide a disabling bias voltage to the gate of the input transistor during power down mode. The output transistor includes a gate, a drain, and a source, wherein the drain of the output transistor is coupled to provide an output of the power amplifier and the source of the output transistor is coupled to the drain of the input transistor.

Abstract: A transformer balun is obtained that is symmetrical in structure, provides high current, or high voltage, amplification and has high coupling coefficients while maintaining minimal overall size. The balun structure includes primary and secondary metal windings at separate layer interfaces. The primary and secondary metal windings are symmetrical and can have any number of turns, which is only limited by integrated circuit area and capacitance. Accordingly, the, primary and secondary windings may be on as many layers as needed. Further, the primary and/or secondary may include a center tap ground, which enables the winding to be used as a differential port.