Abstract: A radio frequency integrated circuit includes a power amplifier, a low noise amplifier, a first transformer balun, and a second transformer balun. The power amplifier includes a first power amplifier section and a second power amplifier section. When enabled, the first and second power amplifier sections amplify an outbound radio frequency (RF) signal to produce a first amplified outbound RF signal and a second amplified outbound RF signal, respectively. The power amplifier provides the first amplified outbound RF signal to the first transformer balun and the second outbound RF signal to the second transformer balun, where the first transformer balun is coupled to a first antenna and the second transformer balun is coupled to a second antenna. The low noise amplifier includes a first low noise amplifier section and a second low noise amplifier section.

Abstract: A mixer includes a reference current source, a programmable gain RF transconductance section or an RF transconductance section, switching quad native transistors or switching quad transistors, and a folded-cascoded common mode output section or an output section. When the mixer included the programmable gain RF transconductance section, the gain of the mixer is adjustable. When the mixer includes the switching quad native transistors, flicker noise of the mixer is reduced. When the mixer includes the folded-cascoded common mode output section, the mixer operates reliably from low supply voltages.

Abstract: A method and apparatus for signal gain adjustment within an RF integrated circuit (IC) include processing that begins by determining the signal strength of a received RF input signal with respect to a first signal strength scale to produce a signal strength indication. The processing continues by determining whether the signal strength indication exceeds a first high power threshold. If not, the receiver continues to process received RF signals without additional attenuation. If, however, the signal strength indication exceeds the first high power threshold, the received RF input signal is attenuated to produce an attenuated RF input signal. In addition, the first signal strength scale is shifted to produce a shifted signal strength scale. The processing continues by determining whether the signal strength of the attenuated RF input signal exceeds a high power threshold of the shifted signal strength scale or is below a low power threshold of the shifted signal strength scale.

Abstract: A method and apparatus for generating a self-correcting local oscillation includes processing that begins by generating a synthesized frequency from a reference frequency. The processing then continues by dividing the synthesized frequency by a divider value to produce a divided frequency. The processing continues by generating an auxiliary frequency and mixing the auxiliary frequency with the divided frequency to produce a corrected frequency. The processing then continues by mixing the corrected frequency with the synthesized frequency to produce a local oscillation.

Abstract: A signal power detector includes an input coupling circuit and a rectifying operational amplifier. The input coupling circuit is operably coupled to receive a signal and to convert the signal into a first input and a rectifying input. The rectifying operational amplifier is operably coupled to receive the first input and the rectifying input and to produce therefrom a rectified output signal that represents a peak of the received signal.

Abstract: Calibration of received signal strength indication (RSSI) within a radio frequency integrated circuit (RFIC) begins by concurrently enables a transmitter portion and receiver portion. With both the transmitter and receiver enabled, the RFIC provides a zero input to the transmitter portion, where the zero input is an effective zero input based on the input circuitry of the transmitter portion. The RFIC then measures, via the receiver portion, the received signal strength of the RF signal generated by the transmitter portion regarding the zero input signal. The RFIC then compares the measured received signal strength with a desired zero input signal strength value. If the measured received signal strength compares unfavorably with the desired zero input signal strength value (e.g.

Abstract: A radio includes a self-calibrating transmitter that uses a portion of a receiver section to perform self-calibration. Accordingly, the radio includes a transmitter section, mixer, analog receiver section, calibration switch module, digital receiver section, calibration determination module, and calibration execution module. The transmitter section produces a modulated RF signal from base-band signal and a transmitter local oscillation. The mixer mixes the modulated RF signal with the transmitter local oscillation to produce a base-band representation of the modulated RF signal. In calibration mode, the calibration switch module provides the base-band representation to the receiver section, which processes the representation to produce a 2nd base-band digital signal. The calibration determination module interprets frequency components of the 2nd base-band digital signal to produce a calibration signal that compensates for imbalances within the transmitter.

Abstract: A differential latch includes a sample transistor section, a hold transistor section, a 1st gating circuit and a 2nd gating circuit. The sample transistor section is operably coupled to sample, when coupled to a supply voltage (e.g., VDD and VSS) a differential input signal. The hold transistor section is operably coupled to latch, when coupled to the supply voltage, the sampled differential input to produce a latched differential signal. The 1st gating circuit is operable to couple the sampled transistor section to the supply voltage in accordance with a 1st clocking logic operation and a 2nd clocking logic operation. The 2nd gating circuit is operable to couple the hold transistor section to the supply voltage in accordance with a 3rd clocking logic operation and a 4th clocking logic operation.

Abstract: An integrated circuit includes electrical components that include one or more electrical elements on one or more dielectric layers. The electrical element has a geometric shape that exceeds prescribed integrated circuit manufacturing limits in at least one dimension. To achieve compliance with foundry rules, the electrical element is fabricated to include a non-conducting region that negligibly effects the electrical characteristics. The non-conducting region includes a hole, a series of holes, a slot and/or a series of slots spaced within the electrical element at dimensions that are less than the integrated circuit manufacturing limits.

Abstract: An integrated low noise amplifier includes an on-chip balun, a line impedance matching circuit and an on-chip differential amplifier. The on-chip balun is operably coupled to convert a single ended signal into a differential signal. The line impedance matching circuit is operably coupled to the primary of the on-chip balun to provide impedance matching for a line carrying the single ended signal. The on-chip differential amplifier is operably coupled to amplify the differential signal and is impedance matched to the secondary of the on-chip balun.

Abstract: A multi-function interface includes a digital interface module, a configurable driver module, and a configurable output impedance module. The digital interface module is operably coupled to pass a 1st type of input signal when the interface is in a 1st mode and operably coupled to pass a 2nd type of input signal when the interface is in a 2nd mode. The configurable driver module is operably coupled to amplify the 1st type of input signal when the interface is in the 1st mode and to amplify the 2nd type of input signal when the interface is in the 2nd mode. The configurable output impedance module is coupled to the configurable driver module to provide a 1st output impedance of the interface when the interface is in the 1st mode and to provide a 2nd output impedance when the interface is in the 2nd mode.

Abstract: A high Q on-chip inductor includes a primary winding and an auxiliary winding that is coupled to receive a proportionally opposite representation of an input of the primary winding. Further, the auxiliary winding has an admittance that is greater than the admittance of the primary winding thereby yielding an asymmetry in the admittances. As such, a push/pull mechanism is obtained in a 2-port system (e.g., 1st and 2nd nodes of the primary winding) that produces a large Q factor for an on-chip inductor.

Abstract: A phase locked loop includes a difference detector, a loop filter, a controlled oscillation module, and a frequency translation module. The difference detector is operably coupled to determine a difference signal based on phase and/or frequency differences between a feedback oscillation and a reference oscillation. The loop filter is operably coupled to generate a control signal from the difference signal. The controlled oscillation module is operably coupled to produce, in accordance with an adjustable operating parameter, an output oscillation based on the controlled signal. The adjustable operating parameter is set based on desired operating conditions of the phase locked loop such that false locking of the phase locked loop is substantially avoided. The frequency translation module is operably coupled to produce the feedback oscillation from the output oscillation based on a frequency translation rate.

Abstract: A programmable mixer includes a 1st mixing stage, a 2nd mixing stage, a coupling element, and a compensation module. The 1st mixing stage is operably coupled to mix one leg of a differential input signal with a differential local oscillation. The 2nd mixing stage is operably coupled to mix the other leg of the differential input with the differential local oscillation. The coupling element couples the 1st and 2nd mixing stages together. The compensation module is operably coupled to the 1st mixing stage and/or the 2nd mixing stage to modify the operational characteristics (e.g., current, impedance, gain, et cetera) of the 1st and/or 2nd mixing stages based on a control signal.

Abstract: A transformer balun is obtained that is symmetrical in structure, provides high current, or high voltage, amplification and has high coupling coefficients while maintaining minimal overall size. The balun structure includes primary and secondary metal windings at separate layer interfaces. The primary and secondary metal windings are symmetrical and can have any number of turns, which is only limited by integrated circuit area and capacitance. Accordingly, the primary and secondary windings may be on as many layers as needed. Further, the primary and/or secondary may include a center tap ground, which enables the winding to be used as a differential port.

Abstract: An on-chip differential multi-layer inductor includes a 1st partial winding on a 1st layer, a 2nd partial winding on the 1st layer, a 3rd partial winding on a 2nd layer, a 4th partial winding on the 2nd layer, and an interconnecting structure. The 1st and 2nd partial windings on the 1st layer are operably coupled to receive a differential input signal. The 3rd and 4th partial windings on the 2nd layer are each operably coupled to a center tap. The interconnecting structure couples the 1st, 2nd, 3rd and 4th partial windings such that the 1st and 3rd partial windings form a winding that is symmetrical about the center tap with a winding formed by the 2nd and 4th partial windings. By designing the on-chip differential multi-layer inductor to have a desired inductance value, a desired Q factor, and a desired operating rate, a desired resonant frequency and corresponding desired capacitance value can be determined.

Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.

Abstract: An on-chip multiple tap transformed balun includes a 1st winding and a 2nd winding having two portions. The 1st winding is on a 1st layer of an integrated circuit and is operably coupled for a single ended signal. The 1st and 2nd portions of the 2nd winding are on a 2nd layer of the integrated circuit. The 1st portion of the 2nd winding includes a 1st node, a 2nd node, and a tap. The 1st node is operably coupled to receive a 1st leg of a 1st differential signal and the 2nd node is coupled to a reference potential. The tap of the 1st portion is operably coupled for a 1st leg of a 2nd differential signal. The 2nd portion of the 2nd winding includes a 1st node, 2nd node, and tap. The 1st node is operably coupled to receive a 2nd leg of the 1st differential signal and the 2nd node is operably coupled to the reference potential. The tap of the 2nd portion is coupled for a 2nd leg of the 2nd differential signal.

Abstract: A differential latch includes a sample transistor section, a hold transistor section, a 1st gating circuit and a 2nd gating circuit. The sample transistor section is operably coupled to sample, when coupled to a supply voltage (e.g., VDD and VSS) a differential input signal. The hold transistor section is operably coupled to latch, when coupled to the supply voltage, the sampled differential input to produce a latched differential signal. The 1st gating circuit is operable to couple the sampled transistor section to the supply voltage in accordance with a 1st clocking logic operation and a 2nd clocking logic operation. The 2nd gating circuit is operable to couple the hold transistor section to the supply voltage in accordance with a 3rd clocking logic operation and a 4th clocking logic operation.

Abstract: A first dynamic logic circuit has an output node on which a scan value is provided during scan. One of one or more second dynamic logic circuits has an input coupled to the output node of the first dynamic logic circuit, and an output of the second dynamic logic circuits is sampled in response to the scan value during scan. In one embodiment, clock generation circuitry may be included which generates a first clock, a second clock, and a third clock. At least one evaluate pulse on the first clock prior is generated prior to sampling the output of the second dynamic logic circuits, the first clock controlling at least the evaluation of the second dynamic logic circuits. The second and third clocks are generated to isolate the output node from inputs to the first dynamic logic circuit responsive to the scan mode signal indicating that scan is active.