Abstract: An MPEG audio/video decoder has memories, a signal processing unit (SPU) including a multiplier and a butterfly unit, a main CPU, and a memory controller which are time division multiplexed between decoding video and audio data. For audio decoding, the butterfly unit determines combinations of components of a frequency-domain vector to reduce the number of multiplies required to transform to the time domain (matrixing). Matrixing is interwoven with MPEG filtering to increase throughput of the decoder by increasing parallel use of the multiplier, the butterfly unit, and a memory controller. A widowing process for the MPEG standard uses only independent components of the audio vectors. This reduces the required number of components to be stored, thereby reducing the size of required memory, the time to write the components after matrixing, and the time to retrieve the components for windowing.

Abstract: A method and apparatus for providing memory arbitration which allows multiple hardware functions implemented in a single ASIC to utilize a single shared memory unit or multiple shared memory units. The memory arbitration technique establishes a priority among multiple memory access requesters and is particularly well-suited for use in a set top box processing system. A plurality of memory access requests are received from a plurality of processing elements in a set top box processing system. The processing elements include a transport stream demultiplexer, a host central processing unit and a graphics processor. The processing elements are permitted to access a shared memory in accordance with an established priority. The established priority assigns a higher priority to the graphics processor than to the host central processing unit, and may be in the order of graphics processor, transport stream demultiplexer, and central processing unit.

Abstract: A selectable reference voltage circuit for a digital-to-analog converter (DAC) which includes an input terminal for receiving an external reference voltage, a voltage comparator having two inputs and an output, one input for receiving the reference voltage and the other for receiving a predetermined voltage, the comparator providing one of two possible output voltages based upon the relationship of the magnitudes of the reference voltage and the predetermined voltage. The circuit includes a multiplexer having a control input coupled to receive as an input signal the output of the comparator, and having two inputs for receiving input voltage signals, one for receiving the voltage on the reference voltage input terminal and the other for receiving an on-chip generated reference voltage, the multiplexer selecting as an output voltage one of the two input voltages determined by the input signal at its control input.

Abstract: A method of retrieving image information is disclosed in which a reference block is selected which overlies three sections of an image stored in a memory having two banks. Exactly two of the sections of the image are stored in the same bank of the memory. A sequence in which to read the three sections is selected such that the two sections in the same bank are not read consecutively. Each section of the image underlying the reference block is read in the selected sequence to retrieve the image information.

Abstract: A rate control algorithm for an MPEG-2 compliant encoder is described. The rate control algorithm has embodiments useful for constant bit rate and variable bit rate encoding. In particular, the invention relates to a field frame macroblock encoding decision.

Abstract: A rate control algorithm for an MPEG-2 compliant encoder is described. The rate control algorithm has embodiments useful for constant bit rate and variable bit rate encoding. In particular, the invention relates to scene change detection.

Abstract: A decoder for compressed video signals comprises a central processing unit (CPU), a dynamic random access memory (DRAM) controller, a variable length code (VLC) decoder, a pixel filter and a video output unit. The microcoded CPU performs dequantization and inverse cosine transform using a pipelined data path, which includes both general purpose and special purpose hardware. In one embodiment, the VLC decoder is implemented as a table-driven state machine where the table contains both control information and decoded values.

Abstract: A method and apparatus for reading and writing data into a random access memory array having a dummy bit. The method includes the steps of providing a clock signal having two edges, one going from low to high and the other going from high to low. The edge going to high from low triggers an enable signal. The enable signal substantially simultaneously triggers a main wordline signal and a dummy wordline signal, the main wordline signal initiating a memory access process while the dummy wordline signal causes the generation of a dummy bit signal from the dummy bit, the combination of the main wordline signal and the dummy bit signal permitting memory access. The dummy bit signal shuts off the enable signal, which in turn causes the memory access process to be terminated and the memory array to go into a bit line precharging stage in preparation for a next read or write cycle, whereby bit line precharging may be commenced prior to the end of the clock cycle.

Abstract: An MPEG audio/video decoder has memories, a signal processing unit (SPU) including a multiplier and a butterfly unit, a main CPU, and a memory controller which are time division multiplexed between decoding video and audio data. For audio decoding, the butterfly unit determines combinations of components of a frequency-domain vector to reduce the number of multiplies required to transform to the time domain (matrixing). Matrixing is interwoven with MPEG filtering to increase throughput of the decoder by increasing parallel use of the multiplier, the butterfly unit, and a memory controller.

Abstract: A rate control algorithm for an MPEG-2 compliant encoder wherein the rate control algorithm has embodiments useful for constant bit rate and variable bit rate encoding. In particular, the present invention relates to statistical multiplexing.

Abstract: A rate control algorithm for an MPEG-2 compliant encoder is described. The rate control algorithm has embodiments useful for constant bit rate and variable bit rate encoding.In particular, the present invention relates to statistical multiplexing.

Abstract: The invention provides methods and apparatus for performing inverse telecine processing on an input video frame sequence to be encoded. A method well-suited for use with mixed video/telecine material in MPEG-2 applications includes the steps of generating a vector of pixel difference scores for a given field in the sequence, dividing each difference score by its smallest adjacent score, filtering the result in a median-like filter, and correlating the divided and filtered scores with a reference vector characteristic of the sequence to generate a correlation metric which is thresholded to provide a field-match indicator for the given field. These steps are repeated for the other fields in the frame sequence, and the resulting repeat field indicators are processed to provide MPEG-2 compliant repeat field codes.

Abstract: A method and structure including four video decompression structures and eight memory banks are provided for decoding high definition television (HDTV) signal. In this HDTV decompression structure, the 1920.times.1080 pixel display space is divided into four vertical sections of 480.times.1080 pixels. Each memory bank stores the values of pixels in one non-overlapping group of 240.times.1080 pixels. Each decompression structure decodes a 480.times.1088-pixel picture area with access to up to two additional 240.times.1088-pixel picture areas. The video decompression structures decode the vertical sections in lock-step to avoid the problem of the same bank of memory being accessed by more than one video decompression structure. In one embodiment of the present invention, a macroblock fetch can cross 1-4 DRAM page boundaries. So, in order to maintain the lock-step relationship of the video decompression structures, each page mode access is limited to fetching only an 8.times.

Abstract: A motion compensation structure and a method are provided for decoding interframe coded video data using motion vectors. The motion compensation structure includes a filter for resampling the pixel data in both vertical and horizontal directions, a prediction memory structure and a weighted adder structure. In one embodiment of the present invention, a weighted adder structure and a method are provided for performing bilinear interpolation of two values using multiplexers and an multiple-input adder.

Abstract: An MPEG audio/video decoder has memories, a signal processing unit (SPU) including a multiplier and a butterfly unit, a main CPU, and a memory controller which are time division multiplexed between decoding video and audio data. The decoder includes a degrouping circuit which performs two divisions in three clock cycles to degroup a subband code. Three cycles matches the write time of three components so that subband codes are degrouped and written to memory with a minimum delay. Performing two divides in three clock cycles allows the divider to be smaller and the decoder to be less expensive.

Abstract: A rate control algorithm for an MPEG-2 compliant encoder is described. The rate control algorithm has embodiments useful for constant bit rate and variable bit rate encoding. In particular, the invention relates to rate control with panic mode.

Abstract: A method and apparatus for performing multi-stage motion estimation on an input video sequence to be encoded. An original image in the video sequence, such as a CCIR601 image, is preprocessed to generate first, second and third reduced resolution images which may be a QQSIF image, a QSIF image and a SIF image, respectively, which are 1/64 size, 1/16 size and 1/4 size, respectively, relative to the original CCIR601 image. A first stage motion vector search is performed on the 1/64 size QQSIF image using a (0,0) motion vector starting point and a first search range suitable for detecting global motion. A second stage motion vector search is performed on the 1/16 size QSIF image using the (0,0) starting point and a second search range smaller than the first search range and suitable for detecting local motion.

Abstract: A rate control algorithm for an MPEG-2 compliant encoder is described. The rate control algorithm has embodiments useful for constant bit rate and variable bit rate encoding. In particular, the invention relates to fade detection.

Abstract: In response to an error signal from a source of an MPEG audio data stream, a decoder replaces data with an error code and temporarily enables error handling. The error code is a valid bit combination rarely found in MPEG audio data frames. During audio decoding with error handling enabled, the decoder checks for the error code and replaces the error code with reconstructed data. Typically, some subband data are replaced with zeros so that an error only changes some of the frequency components.

Abstract: A rate control algorithm for an MPEG-2 compliant encoder is described. The rate control algorithm has embodiments useful for constant bit rate and variable bit rate encoding. In particular, the present invention relates to the overall rate control implementation.