Abstract: A rate control algorithm for an MPEG-2 compliant encoder of the present invention has embodiments useful for constant bit rate and variable bit rate encoding.In particular, the invention relates to a three stage hierarchial motion vector determination.

Abstract: A method and system for performing inverse telecine processing requires a minimum amount of memory capacity. Specifically, the inverse telecine processing technique requires only first and second dual field buffers. The first dual field buffer has a first even buffer (1E) and a first odd buffer (1O). The second dual field buffer has a second even buffer (2E) and a second odd buffer (2O). The input video sequence to be processed comprises a sequence of video fields of alternating even and odd parity. The even fields of the input sequence are written into the even buffers of the two dual field buffers on an alternating basis and the odd fields of the input sequence are written into the odd buffers of the dual field buffers on an alternating basis. This order is changed (i.e., toggled) when a repeat field is detected. The repeat field is dropped by writing over it with the next field of the same parity in the input sequence.

Abstract: A structure and a format for providing a video signal encoder under the MPEG standard are provided. In one embodiment, the video signal interface is provided with a decimator for providing input filtering for the incoming signals. In one embodiment, the central processing unit (CPU) and multiple coprocessors implements DCT and IDCT and other signal processing functions, generating variable length codes, and provides motion estimation and memory management. The instruction set of the central processing unit provides numerous features in support for such features as alpha filtering, eliminating redundancies in video signals derived from motion pictures and scene analysis. In one embodiment, a matcher evaluates 16 absolute differences to evaluate a "patch" of eight motion vectors at a time.

Abstract: A rate control algorithm for an MPEG-2 compliant encoder. The rate control has embodiments useful for constant bit rate and variable bit rate encoding of video frames. The present invention relates to statistical multiplexing, virtual buffers and virtual buffer verifiers.

Abstract: A rate control algorithm for an MPEG-2 compliant encoder is described. The rate control algorithm has embodiments useful for constant bit rate and variable bit rate encoding.In particular, the invention relates to a quantization biased, activity based inter/intra decision.

Abstract: A rate control algorithm for an MPEG-2 compliant encoder is described. The rate control algorithm has embodiments useful for constant bit rate and variable bit rate encoding. In particular, the invention relates to adaptive quantization.

Abstract: A system and method for removing motion artifacts from an interlaced image is disclosed. The interlaced image comprises an odd and an even field. The system and method includes providing one of the odd and the even fields on every other line of the display and then providing a set of constant signal level lines to the remaining lines of the display. The method and system further includes shifting the location of the constant signal levels lines by a scan line responsive to a timing signal from the display, and providing the other of the odd and the even field to the display responsive to the shift.

Abstract: A structure and a format for providing a video signal encoder under the MPEG standard are provided. In one embodiment, the video signal interface is provided with a decimator for providing input filtering for the incoming signals. In one embodiment, the central processing unit (CPU) and multiple coprocessors implements DCT and IDCT and other signal processing functions, generating variable length codes, and provides motion estimation and memory management. The instruction set of the central processing unit provides numerous features in support for such features as alpha filtering, eliminating redundancies in video signals derived from motion pictures and scene analysis. In one embodiment, a matcher evaluates 16 absolute differences to evaluate a "patch" of eight motion vectors at a time.

Abstract: A structure and a format for providing a video signal encoder under the MPEG standard are provided. In one embodiment, the video signal interface is provided with a decimator for providing input filtering for the incoming signals. In one embodiment, the central processing unit (CPU) and multiple coprocessors implements DCT and IDCT and other signal processing functions, generating variable length codes, and provides motion estimation and memory management. The instruction set of the central processing unit provides numerous features in support for such features as alpha filtering, eliminating redundancies in video signals derived from motion pictures and scene analysis. In one embodiment, a matcher evaluates 16 absolute differences to evaluate a "patch" of eight motion vectors at a time.

Abstract: A 2-dimensional display space is mapped into the external DRAM addresses by embedding in the address space X and Y vectors of the display space. The mapping of the X and Y vectors allows a macroblock of pixels to be stored in one DRAM memory page, so that an access to a macroblock can be efficiently accomplished under a page mode access to the DRAM page. By providing control to one address bit, data of four pixels can be obtained at one time in one of 2 pixel.times.2 pixel "quad pixel" configuration, or in a 4 pixel.times.1 pixel horizontal "scan" configuration. In addition, a structure and a method are provided for accessing a 16.times.16-pixel picture area in two parts, in order that the number of DRAM page boundaries crossed during access of the 16.times.16-pixel picture area is minimized, thereby increasing the efficiency of memory access by reducing the overhead cost of initial accesses under page mode access to DRAMs.

Abstract: A structure and a method for providing a video signal encoder under the MPEG-1 and MPEG-2 standards are provided. In one embodiment, a novel scheme for mapping an image to an external memory allows fetching of video data by either field of frame. In addition, an automatic reload of a DMA channel memory allows automatic fetching of an entire 20.times.20 luma reference picture area, or a 12.times.12 chroma reference picture area, while crossing the minimal number of DRAM page boundaries. A novel dequantization instruction in the CPU of the video signal encoder allows efficient oddification of DCT coefficients according to MPEG-1 and MPEG-2 standards.

Abstract: A method and a structure are provided to decode intra-frame and interframe coded compressed video data. In one embodiment of the present invention, a decompression structure having a processor is provided with a global bus over which a decoder coprocessor, an inverse discrete cosine transform coprocessor and a motion compensation coprocessor communicate. The decompression structure in accordance with the present invention communicates with a host computer over a host bus and with an external dynamic random access memory over a memory bus. The processor in the decompression structure of the present invention provides overall control to the decoder, IDCT and motion compensation coprocessors by reading and writing into a plurality of data and control registers, each register associated with one of the decoder, the IDCT and the motion compensation coprocessors.

Abstract: A structure and a format provide a video signal encoder under the MPEG (Motion Picture Experts Group) standard. In one embodiment, the video signal interface is provided with a decimator for providing input filtering for the incoming signals. In one embodiment, the central processing unit (CPU) and multiple coprocessors implements discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) and other signal processing functions, generating variable length codes, and provides motion estimation and memory management. The instruction set of the central processing unit provides numerous features in support for such features as alpha filtering, eliminating redundancies in video signals derived from motion pictures and scene analysis. In one embodiment, a matcher evaluates 16 absolute differences to evaluate a "patch" of eight motion vectors at a time.

Abstract: A structure and a method for providing a video signal encoder under the MPEG-1 and MPEG-2 standards are provided. In one embodiment, a novel scheme for mapping an image to an external memory allows fetching of video data by either field of frame. In addition, an automatic reload of a DMA channel memory allows automatic fetching of an entire 20.times.20 luma reference picture area, or a 12.times.12 chroma reference picture area, while crossing the minimal number of DRAM page boundaries. A novel dequantization instruction in the CPU of the video signal encoder allows efficient oddification of DCT coefficients according to MPEG-1 and MPEG-2 standards.

Abstract: A separate data stream allows encoding of an overlay image, which is to be superimposed on images of a video sequence. The pixels of the overlay image can be transparent or have a text color, a shadow color, or an intermediate color either between the text color and the shadow color, or between the shadow color and the color of the corresponding pixel in the underlying video image. The intermediate colors provide for antialiasing. In addition, a color selection circuit allows selection of the next color from a pool of 9 colors, using a 3-bit field.

Abstract: A structure and a method capable of both packing data into and unpacking data from either the little endian or the big endian format are provided. Under the structure and method of the present invention, the packed or unpacked data, as the case may be, is only shifted in one direction. During a packing operation, a stream of n-bit data is packed into a stream of m-bit words. During an unpacking operation, a stream of m-bit packed data is unpacked into a stream of n-bit words. n.ltoreq.m.

Abstract: A method and a structure are provided to decode intraframe and interframe coded compressed video data. In one embodiment, a decompression structure having a processor is provided with a global bus over which a decoder coprocessor, an inverse discrete cosine transform coprocessor and a motion compensation coprocessor communicate. The decompression structure communicates with a host computer over a host bus and with an external dynamic random access memory over a memory bus. The processor provides overall control to the coprocessors by reading and writing into a plurality of data and control registers, each register associated with one of the coprocessors. A structure including four of the decompression structures and a method are provided for decoding high definition television (HDTV) signals. In this structure for decoding HDTV signals, each decompression structure decodes a 480.times.1088-pixel picture area with access to up to two additional 240.times.1088-pixel picture areas.

Abstract: A digital video compression system and an apparatus implementing this system are disclosed. Specifically, matrices of pixels in the RGB signal format are converted into YUV representation, including a step of selectively sampling the chrominance components. The signals are then subjected to a discrete cosine transform (DCT). A circuitry implementing the DCT in a pipelined architecture is provided. A quantization step eliminates DCT coefficients having amplitude below a set of preset thresholds. The video signal is further compressed by coding the elements of the quantized matrices in a zig-zag manner. This representation is further compressed by Huffman codes. Decompression of the signal is substantially the reverse of compression steps. The inverse discrete cosine transform (IDCT) may be implemented by the DCT circuit. Circuits for implementing RGB to YUV conversion, DCT, quantization, coding and their decompression counterparts are disclosed.

Abstract: In accordance with the present invention, a structure and a method for asynchronously interfacing a master processor and a slave processor is provided by receiving from and providing to the master device control signals of a polling protocol, and receiving from and providing to the slave device control signals of an interrupt type protocol. In a first embodiment of this invention, the master processor provides WR (write request), RD (read request), OE (output enable) signals, and receives a BUSY (busy) signal. The slave processor receives an "int" (interrupt) signal, and provides "intack" (interrupt acknowledge), "outs" (output), and "ins" (input) signals. In a second embodiment of this invention, instead of the RD signal of the first embodiment, the read request signal is the AND product of an AS (address strobe) signal and the most significant bit of the read address.

Abstract: A digital video compression system and an apparatus implementing this system are disclosed. Specifically, matrices of pixels in the RGB signal format are converted into YUV representation, including a step of selectively sampling the chrominance components. The signals are then subjected to a discrete cosine transform (DCT). A circuitry implementing the DCT in a pipelined architecture is provided. A quantization step eliminates DCT coefficients having amplitude below a set of preset thresholds. The video signal is further compressed by coding the elements of the quantized matrices in a zig-zag manner. This representation is further compressed by Huffman codes. Decompression of the signal is substantially the reverse of compression steps. The inverse discrete cosine transform (IDCT) may be implemented by the DCT circuit. Circuits for implementing RGB to YUV conversion, DCT, quantization, coding and their decompression counterparts are disclosed.