Abstract: A fault rules engine generates a plurality of fault rules files. Each of the fault rules files is associated with a respective cell type of a plurality of cell types in an integrated circuit (IC) design, and each fault rules file of the plurality of fault rules files can include data quantifying a nominal delay for a given two-cycle test pattern of a set of two-cycle test patterns and data quantifying a delta delay for the given two-cycle test pattern corresponding to a given candidate defect of a plurality of candidate defects for a given cell type in the IC design. An IC test engine generates cell-aware test patterns based on the plurality of fault rules files to test a fabricated IC chip that is based on the IC design for defects corresponding to a subset of the plurality of candidate defects characterized in the plurality of fault rules files.

Abstract: The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include receiving an electronic design at a verification environment. Embodiments may also include performing a simulation of a portion of the electronic design in an X-propagation mode. Embodiments may further include determining whether the simulation is entering an element during a time range and determining whether a clock/reset associated with the element has an active X-edge. If the clock/reset has an active X-edge, embodiments may include preventing a recordation of coverage metrics during the time range.

Abstract: Embodiments disclosed herein describe systems, methods, and products for safety verification of an IC design. A computer executing an illustrative EDA tool may perform a static cone of influence (COI) analysis of a gate-level netlist of the IC design to determine whether faults injected at combinational logic at different COIs are safe or dangerous. The computer may leverage this determination to perform a register-transfer level (RTL) simulation by generating and injecting equivalent faults to sequential logic in the IC design. The computer may further flexibly allow RTL simulations under different assumptions based upon downstream observability of the faults injected to the sequential logic. Because, RTL simulations are significantly faster than the gate-level simulations, the computer may efficiently calculate DC of one or more safety mechanism in the IC design.

Abstract: A system for optimizing scan pipelining may include a processor and a memory. The processor may generate and insert, based on prior analysis of the physical layout of the circuit, an optimized number of pipeline stages between a first block and a second block in a hardware test design, a first scan chain including at least one pipeline stage of a head pipeline stage or a tail pipeline stage. The processor may insert a plurality of flip-flops into the first scan chain. The processor may determine at least one clock to be used for the at least one pipeline stage, using the plurality of flip-flops so as to eliminate the need of a lockup element between the at least one pipeline stage and the plurality of flip-flops. The processor may generate, based on the at least one clock, a second scan chain that connects the at least one pipeline stage and the plurality of flip-flops.

Abstract: An emulator system and a method for emulating functionalities of an integrated circuit design are disclosed. In one aspect, the system includes a plurality of verification components each comprising circuitry configured to perform transactions with at least another verification component. The system can include a plurality of proxies, each executing on a processor and corresponding to a respective one of the verification components. The system can include a switch that is communicatively coupled with the proxies, the switch dynamically configurable to, in a first time duration, operate with a first subset of the proxies to enable a first transaction between a functional module of the design and a first verification component. The switch can be dynamically configurable to, in a second time duration, operate with a second subset of the proxies to enable a second transaction between the functional module and a second verification component.

Abstract: The embodiments described herein provide for methods and systems for removing power supply induced jitter from a Phase Lock Loop to provide a Power Supply Induced jitter-free clock signal to a system-on-a-chip and GDDR6 DRAM interface. In operation, a circuit reduces a DC offset between a reference voltage and a voltage regulator output to identify low frequency noise on the voltage regulator output to apply as negative feedback to reduce the low frequency noise on the voltage regulator output. The bandwidth of the circuit is increased to detect high frequency noise, which is applied as negative feedback on the voltage regulator output. Very high frequency noise is then detected and applied as negative feedback to the voltage regulator output. The circuit outputs a regulated output equal to the reference voltage and immune to the low, high, and very high frequency noise of power delivery network supply to the regulator.

Abstract: A device may include a plurality of first communication interfaces configured to communicate with a plurality of external client devices, a second communication interface configured to communicate with an external master device, a third communication interface configured to communicate with an external first device, and a first controller. The second communication interface may perform a one-to-many communication with the plurality of first communication interfaces over a first protocol. The third communication interface may communicate with the plurality of first communication interfaces or the second communication interface via the first controller over a second protocol that is different from the first protocol.

Abstract: The present disclosure relates to a computer-implemented method for routing in an electronic design. Embodiments may include receiving, using at least one processor, global route data associated with an electronic design as an input and generating detail route data, based upon, at least in part, the global route data. Embodiments may further include transforming one or more of the detail route data and the global route data into at least one input feature and at least one output result of a deep neural network. Embodiments may also include training the deep neural network with the global route data and the detail route data and predicting an output associated with a detail route based upon, at least in part, a trained deep neural network model.

Abstract: The present disclosure relates to a computer-implemented method for use in an electronic design. Embodiments may include receiving, using at least one processor, a user input corresponding to a command in an electronic design automation environment. Embodiments may further include comparing the user input with a portion of an electronic design database. Embodiments may also include providing a final command suggestion based upon, at least in part, the comparison.

Abstract: The present disclosure relates to an apparatus and method for continuous time linear equalization. Embodiments include a differential amplifier including a first transistor and a second transistor, wherein the differential amplifier includes a peak-generating path and a peak-reduction path. Embodiments also include at least one switch and at least one capacitor located between a source and a drain of at least one of the first transistor and the second transistor to create a capacitive path between the source and drain, wherein the at least one switch and at least one capacitor are configured to reduce bandwidth.

Abstract: An IC chip test engine selects an instrument of an IC design based on an instrument access script, wherein the selected instrument comprises an IP block and a test data register (TDR) logically arranged upstream from the IP block. The IC chip test engine can also identify a set of SIBs gating access to the selected instrument and select a scan chain for operating the set of SIBs to control access to the selected instrument. The IC chip test engine augments the scan chain with data to cause at least a furthest downstream SIB of the set of SIBs that gates access to the selected instrument to transition to an opened state. The IC chip test engine can generate a set of load vectors for the scan chain to load the TDR of the selected instrument with data to apply a respective test pattern to the IP block.

Abstract: The present disclosure relates to electronic circuit design, and more specifically, to determining the computational requirements of fully synthesizing a printed circuit board and/or package. Embodiments may include receiving, using a processor, one or more PCB electronic design files and determining whether the PCB electronic design files include data required for a synthesis engine. If any data is missing, the method may include inferring one or more parameters using an inference engine and providing the one or more parameters to the synthesis engine, wherein the synthesis engine includes at least one of a placement, via assignment, routing, and metal pouring processes. The method may also include collecting process data from the placement, via assignment, routing, and metal pouring processes and training a machine learning system using the process data.

Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving, at a graphical user interface, an indication of a desired wire creation associated with an electronic design and determining a plurality of routing solutions, based upon, at least in part, the desired wire creation. Embodiments may further include simultaneously displaying the plurality of routing solutions at the graphical user interface, wherein a predicted preferred routing solution is graphically emphasized. Embodiments may also include receiving a selection from a user, at the graphical user interface, of one of the plurality of routing solutions and storing the selection for subsequent use.

Abstract: Methods and systems herein can efficiently interconnect processors through a custom grid (a data mesh) utilizing upper metal layer routing in a semiconductor die design to minimize latency. A computer-implemented method of routing interconnects on a semiconductor die includes receiving a set of non-default routes and associated routing rules; identifying a set of critical signals for feedthrough on the set of non-default routes; generating a connectivity matrix including a set of resulting routes, the resulting routes routing the set of critical signals through the set of non-default routes; generating a timing analysis of the connectivity matrix based on a set of latency requirements; responsive to determining that the timing analysis is not compliant with the latency requirements, generating a set of routing constraints; and updating the associated routing rules to include the set of routing constraints.

Abstract: A system for performing operations including accessing an integrated circuit design that includes a clock tree interconnecting a clock source to a plurality of clock sinks. The operations include receiving a request to adjust a current timing offset of the clock tree to a target timing offset. The clock tree is modified by moving a terminal of the group from a first location in the clock tree to a second location in the clock tree to generate an updated clock tree. During modification, the first and second locations are analyzed to determine a load reduction and increase at the respective terminals. One or more neighboring clock tree instances are adjusted to compensate for the load reduction and increase. The operations include providing an indication that the clock tree has been updated and complies with the target timing offset.

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving a printed circuit board schematic and one or more electronic circuits. Embodiments may further include automatically generating, one or more circuit templates based upon, at least in part, the printed circuit board schematic and one or more electronic circuits. The one or more circuit templates may be stored at an electronic design database. Embodiments may also include receiving a current printed circuit board schematic and automatically determining whether a subcircuit of the current printed circuit board schematic is an exact or approximate match with the one or more circuit templates.

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, using a processor, an initial data set associated with an electronic design and performing a built in self-discovery (BISD) analysis based upon, at least in part, the initial data set. Embodiments may include displaying, at a graphical user interface, a plurality of tiered, user-selectable options and receiving a user input corresponding to a selection of at least one of the plurality of tiered, user selectable options. Embodiments may also include tuning the plurality of tiered user selectable options based upon, at least in part, the user input.

Abstract: Various embodiments provide for quarter-rate data sampling with loop-unrolled decision feedback equalization (DFE) that uses a two-summer (e.g., two-summing node) approach. For example, some embodiments provide for quarter-rate data sampling comprising a plurality of unrolled first-tap DFE loops, and two summers and a two-to-one multiplexer for each of the other tap loops used for direct feedback (e.g., second tap, third tap, fourth tap, etc.

Abstract: An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises an initial buffer tree for a net in the IC design. A maximum cost constraint for rebuffering the net is determined based on the initial buffer tree. A partial rebuffering solution is generated for net and a cost associated with the partial rebuffering solution is determined. Based on determining the cost of the partial rebuffering solution satisfies the maximum cost constraint, the partial rebuffering solution is saved in a set of partial rebuffering solutions for the net. A set of candidate rebuffering solutions for the net is generated based on the set of partial rebuffering solutions, and a rebuffering solution for the net is selected from the set of candidate rebuffering solutions. The database is updated to replace the initial buffer tree in the IC design with the rebuffering solution selected for the net.

Abstract: A method of reconstructing an emulated circuit layout for graphical display includes receiving a pre-layout circuit including one or more devices and one or more nodes. The method includes generating a Detailed Standard Parasitic Format (DPSF) netlist representing a post-layout circuit. The DPSF netlist includes a plurality of instances representing the one or more devices, the one or more nodes, and one or more parasitic elements not included in the pre-layout circuit. The method includes identifying at least one node of the one or more nodes that is associated with the one or more parasitic elements. The method includes updating the DPSF netlist to associate the one or more parasitic elements with the at least one node. The method includes constructing graphical representation of the post-layout circuit based on the updated DPSF netlist. The method includes causing a display device to display the graphical representation.