Abstract: Methods and apparatus for frequency offset estimation are disclosed. In an exemplary embodiment, a method includes determining a demodulation reference signal (DMRS) frequency offset estimate from DMRS symbols in a received signal, and determining a cyclic prefix (CP) frequency offset estimate from cyclic prefix values in the received signal. The method also includes combining the DMRS and CP frequency offset estimates to determine a final frequency offset estimate. In an exemplary embodiment, an apparatus includes a DMRS frequency offset estimator that determines a DMRS frequency offset estimate based on DMRS symbols received in an uplink transmission, and a cyclic prefix (CP) frequency offset estimator that determines a CP frequency offset estimate based on cyclic prefix values in the uplink transmission. The apparatus also includes an offset combiner that combines the DMRS frequency offset estimate with the CP frequency offset estimate to generate a final frequency offset estimate.

Abstract: Method and system embodying the method for a direct memory access between a data storage and a data processing device via one or more direct memory access units, comprising transferring data between the data storage and a first direct memory access engine of a respective one or more direct memory access units and providing the data for a second direct memory access engine of the respective one or more direct memory access units; and transferring the data provided by the first direct memory access engine by a second direct memory access engine to the data processing device via the second direct memory access engine is disclosed.

Abstract: Methods and apparatus for channel detection in an uplink shared control channel. In an exemplary embodiment, a method includes generating soft-combined bit streams for an acknowledgement (ACK) indicator, rank indicator (RI), and channel quality indicator (CQI) received in an uplink shared channel. The method also includes decoding the ACK, RI, and CQI soft-combined bit streams to generate Top-M decoded bit streams for each indicator, and generating Top-Q symbols for each indicator from the Top-M decoded bit streams for each indicator. The method also includes calculating metrics from the Top-Q symbols and uplink control information (UCI) symbols extracted from the uplink shared channel, combining the metrics to form a search space, and searching the search space to determine transmitted ACK, RI, and CQI bits.

Abstract: A vector memory subsystem for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes a vector memory bank and a vector memory system (VMS) that generates input memory addresses that are used to store input data into the vector memory bank. The VMS also generates output memory addresses that are used to unload vector data from the memory banks. The input memory addresses are used to shuffle the input data in the memory bank based on a radix factorization associated with an N-point DFT, and the output memory addresses are used to unload the vector data from the memory bank to compute radix factors of the radix factorization.

Abstract: Methods and apparatus for job scheduling in a programmable mixed-radix DFT/IDFT processor. In an exemplary embodiment, a method includes receiving a plurality of discrete Fourier transform (DFT) jobs. Each job identifies a computation of a DFT of a particular point size. The method also includes bundling selected jobs having a selected point size into a mega-job, and identifying a radix factorization for the selected point size. The radix factorization includes one or more stages and each stage identifies a radix computation to be performed. The method also includes computing, for each stage, the identified radix computations for the selected jobs in the mega-job. The radix computations for each stage are performed for the selected jobs before performing radix computations for a subsequent stage. The method also includes outputting DFT results for the selected jobs in the mega-job.

Abstract: Methods and apparatus for dynamic acknowledgement list selection in detection of uplink control channel formats. In an exemplary embodiment, an apparatus includes a dynamic acknowledgement (ACK) list allocation circuit that generates a dynamic ACK list that includes one or two most likely ACK candidates, and a top-Q candidate CQI bits detector that dynamically allocates a detection branch to each of the one or two most likely ACK candidates to detect top-Q candidate CQI bits. The apparatus also includes a merger circuit that mergers the top-Q candidate CQI bits detected for the one or two most likely ACK candidates to generate a merged list, a top-Q CQI symbol generator that generates top-Q CQI symbols for the top-Q candidate CQI bits detected for the one or two most likely ACK candidates, and a joint detector that detects transmitted CQI bits and ACK bits.

Abstract: Methods and apparatus for job scheduling in a programmable mixed-radix DFT/IDFT processor. In an exemplary embodiment, a method includes receiving a plurality of discrete Fourier transform (DFT) jobs. Each job identifies a computation of a DFT of a particular point size. The method also includes bundling selected jobs having a selected point size into a mega-job, and identifying a radix factorization for the selected point size. The radix factorization includes one or more stages and each stage identifies a radix computation to be performed. The method also includes computing, for each stage, the identified radix computations for the selected jobs in the mega-job. The radix computations for each stage are performed for the selected jobs before performing radix computations for a subsequent stage. The method also includes outputting DFT results for the selected jobs in the mega-job.

Abstract: Methods and apparatus for providing a demapping system to demap uplink transmissions. In an embodiment, a method is provided that includes detecting a processing type associated with a received uplink transmission, and when the detected processing type is a first processing type then performing the following operations: removing resource elements containing reference signals from the uplink transmission; layer demapping remaining resource elements of the uplink transmission into two or more layers; soft-demapping the two or more layers to produce soft-demapped data. The method also includes descrambling the soft-demapped data to produce descrambled data, and processing the descrambled data to generate uplink control information (UCI).

Abstract: A vector memory subsystem for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes a vector memory bank and a vector memory system (VMS) that generates input memory addresses that are used to store input data into the vector memory bank. The VMS also generates output memory addresses that are used to unload vector data from the memory banks. The input memory addresses are used to shuffle the input data in the memory bank based on a radix factorization associated with an N-point DFT, and the output memory addresses are used to unload the vector data from the memory bank to compute radix factors of the radix factorization.

Abstract: Methods and apparatus for dynamic acknowledgement list selection in detection of uplink control channel formats. In an exemplary embodiment, an apparatus includes a dynamic acknowledgement (ACK) list allocation circuit that generates a dynamic ACK list that includes one or two most likely ACK candidates, and a top-Q candidate CQI bits detector that dynamically allocates a detection branch to each of the one or two most likely ACK candidates to detect top-Q candidate CQI bits. The apparatus also includes a merger circuit that mergers the top-Q candidate CQI bits detected for the one or two most likely ACK candidates to generate a merged list, a top-Q CQI symbol generator that generates top-Q CQI symbols for the top-Q candidate CQI bits detected for the one or two most likely ACK candidates, and a joint detector that detects transmitted CQI bits and ACK bits.

Abstract: Methods and apparatus for job scheduling in a programmable mixed-radix DFT/IDFT processor. In an exemplary embodiment, a method includes receiving a plurality of discrete Fourier transform (DFT) jobs. Each job identifies a computation of a DFT of a particular point size. The method also includes bundling selected jobs having a selected point size into a mega-job, and identifying a radix factorization for the selected point size. The radix factorization includes one or more stages and each stage identifies a radix computation to be performed. The method also includes computing, for each stage, the identified radix computations for the selected jobs in the mega-job. The radix computations for each stage are performed for the selected jobs before performing radix computations for a subsequent stage. The method also includes outputting DFT results for the selected jobs in the mega-job.

Abstract: Methods and apparatus for two-stage ACK/DTX detection. In an embodiment, a method includes determining a first stage DTX value from bit-domain correlation values, and determining a second stage DTX value from symbol domain correlation values generated from candidate ACK bits. The method also includes determining a DTX decision based on the first stage DTX value and the second stage DTX value.

Abstract: Twiddle factor generation for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes look-up table logic that receives twiddle control factors and outputs a selected twiddle factor scaler value (TFSV), a base vector generator that generates a base vector values based on the selected TFSV, and a twiddle column generator that generates a twiddle vector from the base vector.

Abstract: Embodiments of the present invention relate to a Lookup and Decision Engine (LDE) for generating lookup keys for input tokens and modifying the input tokens based on contents of lookup results. The input tokens are parsed from network packet headers by a Parser, and the tokens are then modified by the LDE. The modified tokens guide how corresponding network packets will be modified or forwarded by other components in a software-defined networking (SDN) system. The design of the LDE is highly flexible and protocol independent. Conditions and rules for generating lookup keys and for modifying tokens are fully programmable such that the LDE can perform a wide variety of reconfigurable network features and protocols in the SDN system.

Abstract: Methods and systems for network devices are provided. One method includes receiving a frame by a network device communicating with a computing device via a peripheral link, the network device receiving the frame via a network connection; using one or more frame header fields to generate a frame context by the network device; determining if a processor of the network device is processing another frame with the same frame context; assigning the frame context to a first processor of the network device, when the first processor is processing the other frame with the same frame context; and when neither processor is processing the same frame context, selecting between the first processor and a second processor of the network device, based on a workload of the first processor and the second processor, the workload determined by a number of contexts that are pending for the first processor and the second processor.

Abstract: Method and system embodying the method for load balancing of scheduled jobs among a plurality of engines encompassing determining a number of cluster credits for each of a plurality of clusters that comprise at least one engine capable of processing a scheduled job; determining a number of engine credits for each of the plurality of engines comprising each of the at least one engine in accordance with a number of jobs assigned to each of the plurality of engines; evaluating the determined number of cluster credits and the determined number of engine credits in accordance with a credit evaluation policy; and assigning the job to one of the plurality of engines in accordance with the evaluation, is disclosed.

Abstract: Methods and apparatus for frequency offset estimation are disclosed. In an exemplary embodiment, a method includes determining a demodulation reference signal (DMRS) frequency offset estimate from DMRS symbols in a received signal, and determining a cyclic prefix (CP) frequency offset estimate from cyclic prefix values in the received signal. The method also includes combining the DMRS and CP frequency offset estimates to determine a final frequency offset estimate. In an exemplary embodiment, an apparatus includes a DMRS frequency offset estimator that determines a DMRS frequency offset estimate based on DMRS symbols received in an uplink transmission, and a cyclic prefix (CP) frequency offset estimator that determines a CP frequency offset estimate based on cyclic prefix values in the uplink transmission. The apparatus also includes an offset combiner that combines the DMRS frequency offset estimate with the CP frequency offset estimate to generate a final frequency offset estimate.

Abstract: A network switch capable of supporting cut-though switching and interface channelization with enhanced system performance. The network switch includes a plurality of ingress tiles, each tile including a virtual output queue (VOQ) scheduler operable to submit schedule requests to a fabric scheduler. Data is requested in unit of quantum which may aggregate multiple packets, which reduces schedule latency. Each request is associated with a start-of-quantum (SoR) state or a middle-of-quantum (MoR) state to support cut-through. The fabric scheduler performs a multi-stage scheduling process to progressively narrow the selection of requests, including stages of arbitration in virtual output port level, virtual output port group level, tile level, egress port level and port group level. Each tile receives the grants for its requests and accordingly sends request data to a switch fabric for transmission to the destination egress ports.

Abstract: One aspect of the present invention discloses a network system capable of transmitting and processing audio video (“A/V”) data with enhanced quality of service (“QoS”). The network system includes a transmitter, a transmission channel, an adjustable decoder buffer, and a decoder. The transmitter contains an encoder able to encode A/V data in accordance with encoding bit rate recommendation from SQoS and packets loss notifications. The transmission channel, in one example, transmits A/V data from the transmitter or the receiver. The adjustable decoder buffer, in one aspect, is able to change its storage capacity or buffering size in response to the adaptive latency estimate. Upon fetching at least a portion of the A/V data from the adjustable decoder buffer, SQoS updates the adaptive latency estimate based on the quality of the decoded A/V data.

Abstract: An ALU capable of generating a multiply accumulation by compressing like-magnitude partial products. Given N pairs of multiplier and multiplicand, Booth encoding is used to encode the multipliers into M digits, and M partial products are produced for each pair of with each partial product in a smaller precision than a final product. The partial products resulting from the same encoded multiplier digit position, are summed across all the multiplies to produce a summed partial product. In this manner, the partial product summation operations can be advantageously performed in the smaller precision. The M summed partial products are then summed together with an aggregated fixup vector for sign extension. If the N multipliers are equal to a constant, a preliminary fixup vector can be generated based on a predetermined value with adjustment on particular bits, where the predetermined value is determined by the signs of the encoded multiplier digits.