Abstract: A multicast destination table contains a list of links. The list of links includes the main link that is currently in use and alternate links to reach the same destination. The links in the list of links are ordered based on a metric. Each of the links is stored as an entry in the multicast destination table. A multicast replication engine traverses the list of links until an enabled link in the list of links is reached, and replicates a packet according to data associated with the enabled link in the list of links.

Abstract: Execution of the memory instructions is managed using memory management circuitry including a first cache that stores a plurality of the mappings in the page table, and a second cache that stores entries based on virtual addresses. The memory management circuitry executes operations from the one or more modules, including, in response to a first operation that invalidates at least a first virtual address, selectively ordering each of a plurality of in progress operations that were in progress when the first operation was received by the memory management circuitry, wherein a position in the ordering of a particular in progress operation depends on either or both of: (1) which of one or more modules initiated the particular in progress operation, or (2) whether or not the particular in progress operation provides results to the first cache or second cache.

Abstract: Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock stored in a particular memory location, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts using associated operation messages for accessing the particular memory location, or (2) an unlock operation corresponding to a particular lock stored in a particular memory location, releasing the particular lock from the first thread using an associated operation message for accessing the particular memory location. Selected operation messages associated with an unlock operation are prioritized over operation messages associated with a lock operation.

Abstract: A vector memory subsystem for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes a vector memory bank and a vector memory system (VMS) that generates input memory addresses that are used to store input data into the vector memory bank. The VMS also generates output memory addresses that are used to unload vector data from the memory banks. The input memory addresses are used to shuffle the input data in the memory bank based on a radix factorization associated with an N-point DFT, and the output memory addresses are used to unload the vector data from the memory bank to compute radix factors of the radix factorization.

Abstract: A data recovery circuit provides compensation for baseline wander exhibited by a data signal. An adaptive equalizer generates a recovered data signal from a data input. A level shifter and low-pass filter provide a compensation signal as a function of the recovered data signal. An adaptation engine adjusts the level of the compensation signal to compensate for baseline wander. The adaptive equalizer generates the recovered data signal as a function of the data input and the compensation signal, thereby providing accurate recovery of the data signal.

Abstract: A vector memory subsystem for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes a vector memory bank and a vector memory system (VMS) that generates input memory addresses that are used to store input data into the vector memory bank. The VMS also generates output memory addresses that are used to unload vector data from the memory banks. The input memory addresses are used to shuffle the input data in the memory bank based on a radix factorization associated with an N-point DFT, and the output memory addresses are used to unload the vector data from the memory bank to compute radix factors of the radix factorization.

Abstract: Systems and methods for inserting flops at the chip-level to produce a signal delay for preventing buffer overflow are disclosed herein. Shells of modules described in an RTL description and their connections are analyzed to determine a signal latency between a sender block and a receiver block. The logical interfaces of the shells are grouped in a structured document with associated rules. Flops are inserted between the sender block and the receiver block to introduce a flop delay to meet physical design timing requirement and prevent a buffer of the receiver block from overflowing due to data that is already in-flight when a flow control signal is sent by the receiver block. The sum of a delay on a data line and a delay on a flow control line measured in clock cycles must be less than a depth of the buffer.

Abstract: In an embodiment, a method of providing quality of service (QoS) to at least one resource of a hardware processor includes providing, in a memory of the hardware processor, a context including at least one quality of service parameter and allocating access to the at least one resource of the hardware processor based on the quality of service parameter of the context, a device identifier, a virtual machine identifier, and the context.

Abstract: A computer-implemented medium using a scheduler for processing requests by receiving packet data from multiple source ports and then classifying, the received packet data based upon the source port received and a destination port the data being sent. Next, sorting, the classified packet data into multiple queues in a buffer, and updating, a static component of one or more of the multiple queues upon the queue receiving the sorted classified data packet. Further, scheduling, using the scheduler based upon the destination port availability and a set of fairness factors including priority weights and positions, for selecting a dequeuing of data packets from a set of corresponding queues of the multiple queues, and then updating the static of the dequeued queue upon the data packet being outputted from the dequeued queue.

Abstract: A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.

Abstract: A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a plurality of primary interfaces thereby forming a unidirectional client chain. This chain is then able to be utilized by all of the hierarchical clients to write the packet data to or read the packet data from the packet memory.

Abstract: Methods and apparatus for simultaneous multiprotocol processing of different radio standards using a common pipeline. In an exemplary embodiment an apparatus includes a plurality of wireless interfaces that transmit radio data symbols, a scheduler that outputs scheduled events that control transmission of the radio data symbols using any wireless interface type and any radio protocol, and an event processor that processes the transmission events to transport the radio data symbols to selected wireless interfaces for over the air transmission using selected radio protocols.

Abstract: Partition information includes entries that each include an entity identifier and associated cache configuration information. A controller manages memory requests originating from processor cores, including: comparing at least a portion of an address included in a memory request with tags stored in a cache to determine whether the memory request results in a hit or a miss, and comparing an entity identifier included in the memory request with stored entity identifiers to determine a matched entry. The cache configuration information associated with the entity identifier in a matched entry is updated based at least in part on a hit or miss result. The associated cache configuration information includes cache usage information that tracks usage of the cache by an entity associated with the particular entity identifier, and partition descriptors that each define a different group of one or more of the regions.

Abstract: A software and hardware co-validation for SDN SoC method and system are able to be used to test software and hardware using PCIe (or another implementation) utilizing sockets and messages as the communication medium. An entire software stack as well as hardware are able to be tested. Additionally, multiple chips (SoCs) are able to be programmed at the same time, not just one, as in previous implementations.

Abstract: A method for parsing network packets via one or more clusters configured to parse network packets comprises receiving one or more packets to be parsed; determining a candidate cluster of the one or more clusters for parsing the one or more packets; transmitting the one or more packets to the candidate cluster; launching the candidate cluster to parse the one or more packets when a launch condition is met; and receiving parse results for the one or more packets from the candidate cluster. The launch condition may be met after transmitting the one or more packets meets a fraction of a parsing capacity of the candidate cluster. The fraction may be one such that the transmitting the one or more packets meets a parsing capacity of the candidate cluster. The launch condition may also be met when a time elapsed since a previous cluster was launched reaches a delay limit.

Abstract: In one embodiment, a system includes a data navigation unit configured to navigate through a data structure stored in a first memory to a first representation of at least one rule. The system further includes at least one rule processing unit configured to a) receive the at least one rule based on the first representation of the at least one rule from a second memory to one of the rule processing unit, and b) processing a key using the at least one rule.

Abstract: Methods and systems for a computing device and an adapter are provided. One method includes allocating a memory location at the adapter for storing messages logged by a driver during a pre-boot operation of an operating system of the computing device coupled to the driver; generating a variable by the driver executed by the computing device, the variable includes an address of the memory location and is identified by a unique identifier; using a first application programming interface (API) by the driver for enabling message logging at the memory location during the pre-boot operation; retrieving the address of the memory location by a second API using the unique identifier of the variable; and obtaining by the second API on behalf of an application executed by the computing device, a message logged at the memory location by the driver during the pre-boot operation.

Abstract: In some embodiments, the circuits (and methods) may include a reference generator configured to generate a reference signal. The circuits (and methods) may also include a signal presence detection module configured to perform calibration on itself, during a calibration phase, based upon the reference signal. The signal presence detection module may be further configured to receive an input signal. The signal presence detection module may be further configured to perform detection, during a signal amplitude detection phase, of a state of the input signal. According to some embodiments, the circuits (and methods) may include a peak detector of the signal presence detection module shared by the calibration and the detection. In some embodiments of the circuits (and methods), the reference generator may be unpowered during the signal amplitude detection phase. The calibration and the detection may share the peak detector based upon time division multiplexing.

Abstract: Managing instructions on a processor includes: executing threads having access to a stored library of operations. For a first thread executing on the first processor core, for each instruction included in the first thread and identified as being associated with a lock operation corresponding to a particular lock, the managing includes determining if the particular lock has already been acquired for another thread executing on a processor core other than the first processor core, and if so, continuing to perform the lock operation for multiple attempts using a hardware lock operation different from the lock operation in the stored library, and if not, acquiring the particular lock for the first thread. The hardware lock operation performs a modified atomic operation that changes a result of the hardware lock operation for failed attempts to acquire the particular lock relative to a result of the lock operation in the stored library.

Abstract: A new approach is proposed that contemplates systems and methods to support a mechanism to offload IPSec/IKE processing of virtual machines (VMs) running on a host to an embedded networking device, which serves as a hardware accelerator for the VMs that need to have secured communication with a remote device/server over a network. By utilizing a plurality of its software and hardware features, the embedded networking device is configured to perform all offloaded IPSec operations on data packets transferred between the host and the remote device over the network as required for the secured communication before the data packets can be transmitted over the network. The embedded networking device, in effect, acts as a proxy on behalf of the VMs running on the host to perform the offloaded IPSec operations as well as serving as the network interface for the secured communication between the VMs and the remote device.