Abstract: Frame synchronization is accomplished in a trellis-coded communication system by causing the sequence of signal points that results when the receiver incorrectly determines the start of each frame to be an impermissible sequence, and detecting the existence of the impermissible sequence by monitoring the rate of occurrence of non-zero difference between the minimum branch metric and the minimum path metric of a maximum likelihood decoding algorithm, such as the Viterbi decoding algorithm. In another aspect, an interleaver and a deinterleaver are used to assure that impermissible sequences result when frame synchronization is lost.

Abstract: A receiver for use in deciding which signal points were sent from a transmitter based on corresponding noise affected signals received over a channel, the transmitter including an encoder which encodes a stream of information symbols into the signal points, the noise affected signals carrying information about a particular sequence of possible states occupied in a succession of time intervals by a finite state process. The receiver includes feedback circuitry for generating a plurality of different modified versions of each received signal, and a decoder for deciding which signal points were sent, given the received signals, based on estimating the particular sequence of states, and using at least two different modified versions.

Abstract: A logic array which is small in size and low in power dissipation uses only one clock signal. The array is fully precharged by precharging a first portion and a second portion and then applying ground to the first portion while delayably applying the ground to the second portion. The address is read into the first portion during the precharging to speed up operation of the array.

Abstract: A data communication network over which data handling devices can transmit and receive packets among themselves having a bus, a number of subnetworks (each having interfaces for connecting a number of devices to each subnetwork), a concentrator for connecting each interface to the bus, each concentrator having a transceiver for transmitting, to the bus and to devices connected to each subnetwork, packets originating from devices within a subnetwork (transmitted packets), and for receiving from the bus packets originating from other subnetworks (received packets), collision avoidance circuitry for monitoring transmission attempts by devices connected to the subnetwork, for detecting competing transmission attempts that would create a collision on the subnetwork, and, upon such detection, permitting a selected attempt to enter the subnetwork, while preventing other attempts from entering it, collision detection circuitry for monitoring the bus and preventing all attempted transmissions from entering the bus whe

Abstract: A two-pass Multiplier/Accumulator Circuit is provided which performs various arithmetic operations on operands contained within an X Register 10 (FIG. 1) and a Y Register 20 and places the result in an Accumulator Register 40. The arithmetic operations are carried out by passing the product of the operands successively through an array of adders in the Adder unit 34. Each adder adds an appropriate multiple of the contents of the X Register to the Accumulator 40 or to the output of the previous adder. The multiples are selected according to the contents of the Y Register.The X and Y Registers are fully buffered so that additional data transfers and functions may be performed while an arithmetic operation is in progress in a "pipeline" manner.The circuit is also capable of indicating the maximum or minimum value in a sequence of numbers in response to a single computer instruction to the circuit.

Abstract: An improvement to a modulation system of the kind in which the encoder selects a codeword corresponding to a plurality of modulation signal points on the basis of a block of digital data, the available codewords for a given block being independent of the signal points corresponding to the codeword selected for any other block. In the improvement a constellation of available signals comprises groups with equal numbers of signals, and an encoder is arranged so that the group from which at least one signal point for a block is drawn depends on the group from which at least one other signal point for the block is drawn. In another aspect, the constellation includes inner signals and outer signals, one bit of data determines whether any of the signal points will be outer signals, and if so at least one other bit determines which will be an outer signal point.

Abstract: Apparatus for sending bits of information over a band-limited channel by modulating a carrier in accordance with a sequence of signal points drawn from a constellation of available signal points, in which the apparatus includes circuitry for accumulating groups of the information bits for encoding into the signal points, different groups having different numbers of information bits from a primary data source, and an encoder for encoding at least the bits of each said group into at least one signal point drawn from the constellation, the encoder being arranged to draw different available signal points with different probabilities.

Abstract: In one aspect the invention features a digital synthesizer having clock circuitry to provide a clock pulse train, synthesizer circuitry to provide a synthesized pulse train at a frequency such that multiple clock pulses occur between pairs of successive synthesized pulses, and phase control circuitry to cause an effective shift in the synthesized pulse train frequency by causing, between pairs of successive synthesized pulses, a number of phase shifts in the clock pulse train.

Abstract: In apparatus for transmitting digital symbols over a band-limited channel using a modulated carrier system by encoding the symbols into discrete signals selected by a finite state encoder from a signal alphabet comprised of subsets each corresponding to transitions from a particular previous state to a particular current state of the encoder, the improvement in which at least two of the subsets have a signal in common, and at least one signal belongs to only one of the two subsets.

Abstract: A stream of source characters, which occur with varying relative frequencies, is encoded into a compressed stream of codewords, each having one, two or three subwords, by ranking the source characters by their current frequency of appearance, encoding the source characters having ranks no higher than a first number as one sub-word codewords, source characters having ranks higher than the first number but no higher than a second number as two sub-word codewords, and the remaining source characters as three sub-word codewords. The first number is changed and the second number is recalculated as required by the changing frequencies of the source characters to minimize the length of the stream of codewords.

Abstract: A stream of source characters, which occur with varying relative frequencies, is encoded into a compressed stream of codewords, each having one, two or three subwords, by ranking the source characters by their current frequency of appearance, encoding the source characters having ranks no higher than a first number as one sub-word codewords, source characters having ranks higher than the first number but no higher than a second number as two sub-word codewords, and the remaining source characters as three sub-word codewords. The first number is changed and the second number is recalculated as required by the changing frequencies of the source characters to minimize the length of the stream of codewords.

Abstract: A driver circuit directly couples the clock signal to gate electrodes of pull-up devices to minimize the loading effect on the clock signal. The pull-up devices pull up the output to substantially the positive power supply voltage. The clock signal is coupled to the gate electrodes of the pull-up devices by a transistor whose gate electrode is controlled by a control signal. The control signal also triggers the pull down of the gate electrode of the pull-up devices when it is not desired to couple the clock signal to the gate electrode of the pull-up devices.

Abstract: Apparatus for regulating access by each of a plurality of asynchronous data processors to each of a plurality of memories, each processor being associated with one of the memories and needing both read and write access to its own memory and to the processor's memories, the apparatus including local bus circuitry to selectably permit each processor to have, or to prevent each processor from having, access to its associated memory, connecting bus circuitry to selectably permit each processor to have, or to prevent each processor from having, direct access to the other processors' memories, and control circuitry for giving each requesting processor access over the connecting bus to another processor's memory, and for giving each processor access over the local bus circuitry to its own memory except when access to its own memory is being given to another one of the processors.

Abstract: In modem apparatus having receiver circuitry which demodulates a received carrier into a sequence of received signals and decodes each signal into a signal point drawn from a predetermined signal point alphabet, the received carrier being modulated in accordance with a sequence of signal points representing a message, that improvement having circuitry for estimating the receipt of the end of the message by testing each received signal against a predetermined end-of-message condition.

Abstract: Independent loading and first-in, first-out reading of a sequence of data words in a data store is controlled by pointers which independently indicate the next-to-be-loaded and next-to-be-read stages in the data store, the pointers being updated after each loading and reading; half-full flag circuitry indicates when at least half of the stages are occupied; and the number of stages available for storing can be selectably changed.

Abstract: In a programmable machine, a combination for executing a do loop without requiring "overhead" steps to be included in the do loop, having means for determining when the final do loop step is being executed, means for counting the number of do loop iterations remaining, and means for proceeding to the first do loop step each time the final do loop step is being executed provided the last iteration has not been reached, or otherwise for exiting from the do loop.

Abstract: Modem apparatus in which a modulated carrier signal represents digital bits, wherein the apparatus includes first digital processing circuitry having first programmable digital circuitry for arithmetic manipulation of digital values in accordance with selectable arithmetic program instructions to produce a correspondence between a sequence of signal values at a rate of 1/T signal values per second and a sequence of samples at a rate higher than 1/T samples per second representing the modulated carrier signal, where T represents the duration of a modulation period of the carrier signal, first bus circuitry connected to the first programmable digital circuitry for carrying the digital values and the arithmetic program instructions, and first memory circuitry connected to the first bus circuitry for storing the instructions, digital values, and signal values; second digital processing circuitry comprising second programmable digital circuitry for generating control signals corresponding to predetermined sequence

Abstract: Automatic gain control circuitry in a modem receiver, featuring a digitally controlled gain element for imposing on the received modulated carrier signal a gain corresponding to gain control signals g received from a microprocessor, an analog-to-digital converter to provide the microprocessor with digital samples of the received modulated carrier signal, and a gain control in the microprocessor for comparing an estimate of the average level of the samples with a desired level, and generating the control signals g based on the result of the comparison.

Abstract: An improved linear phase digital filter for filtering a data signal, featuring, in one aspect, means for storing samples of the signal on two delay lines which, when cycled, provide pairs of samples whose member sample sequences are oppositely time ordered.

Abstract: In modem circuitry in which an angle modulated carrier signal is clipped and demodulated, and the demodulated signal is filtered and compared with a threshold value to produce an output signal, the invention features, in one aspect, a delay line whose length and shifting frequency are both programmable and, in another aspect, the combination of a differential detector, having a programmable delay line and a digital filter, having a programmable sampling frequency.