Patents Assigned to Coherent Logix, Incorporated
  • Patent number: 11914989
    Abstract: Techniques for specifying and implementing a software application targeted for execution on a multiprocessor array (MPA). The MPA may include a plurality of processing elements, supporting memory, and a high bandwidth interconnection network (IN), communicatively coupling the plurality of processing elements and supporting memory. In some embodiments, software code may specify one or more cell definitions that include: program instructions executable to perform a function and one or more language constructs. The software code may further instantiate first, second, and third cell instances, each of which is an instantiation of one of the one or more cell definitions, where the instantiation includes configuration of the one or more language constructs such that: the first and second cell instances communicate via respective communication ports and the first and second cell instances are included in the third cell instance.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: February 27, 2024
    Assignee: Coherent Logix, Incorporated
    Inventors: Stephen E. Lim, Viet N. Ngo, Jeffrey M. Nicholson, John Mark Beardslee, Teng-I Wang, Zhong Qing Shang, Michael Lyle Purnell
  • Patent number: 11910200
    Abstract: A broadcast/broadband convergence system that delivers content from content sources to user equipment devices. The system provides: significantly enhanced mobile capability to the broadcast industry; an additional revenue source for the broadcast industry by dynamically selling available spectral resources for use by wireless broadband networks and/or broadcast content off-loaded from wireless broadband networks; additional spectrum for the broadband industry through the dynamic purchase of available spectrum; and an enriched user experience. A spectrum server may facilitate the dynamic allocation of radio spectrum made available by the broadcast networks. The broadcast networks may broadcast with enhanced waveform parameters to support mobile devices as well as fixed devices.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: February 20, 2024
    Assignee: Coherent Logix, Incorporated
    Inventors: Tommy K. Eng, Kevin A. Shelby
  • Patent number: 11900124
    Abstract: Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. First and second address generator units may generate, based on different fields of the multi-part instruction, addresses from which to retrieve first and second data for use by an execution unit for the multi-part instruction or a subsequent multi-part instruction. The execution units may perform operations using a single pipeline or multiple pipelines based on third and fourth fields of the multi-part instruction.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: February 13, 2024
    Assignee: Coherent Logix, Incorporated
    Inventors: Michael B Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, Kenneth R. Faulkner, Keith M. Bindloss, Sumeer Arya, John Mark Beardslee, David A. Gibson
  • Patent number: 11849130
    Abstract: Methods and devices for a parallel multi-processor encoder system for encoding video data. The video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system divides the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks is transmitted to the decoder for each processor prior to transmission of the next sequential respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: December 19, 2023
    Assignee: Coherent Logix, Incorporated
    Inventors: Michael W. Bruns, Martin A. Hunt, Manjunath H. Siddaiah, John C. Sievers
  • Patent number: 11829320
    Abstract: A multi-processor system with processing elements, interspersed memory, and primary and secondary interconnection networks optimized for high performance and low power dissipation is disclosed. In the secondary network multiple message routing nodes are arranged in an interspersed fashion with multiple processors. A given message routing node may receive messages from other message nodes, and relay the received messages to destination message routing nodes using relative offsets included in the messages. The relative offset may specify a number of message nodes from the message node that originated a message to a destination message node.
    Type: Grant
    Filed: October 20, 2022
    Date of Patent: November 28, 2023
    Assignee: Coherent Logix, Incorporated
    Inventors: Carl S. Dobbs, Keith M. Bindloss, Kenneth R. Faulkner, Alex E. Icaza, Frederick A. Rush, Faisal A. Syed, Michael R. Trocino
  • Patent number: 11755504
    Abstract: Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: September 12, 2023
    Assignee: Coherent Logix, Incorporated
    Inventors: Carl S. Dobbs, Michael R. Trocino
  • Patent number: 11755382
    Abstract: Various embodiments are disclosed of a compilation with optimization for multi-processor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Application source code may be initially compiled into an intermediate representation. Following the initial compilation, resources may be mapped and communication synthesis performed. Simulation and debug may be performed prior to loading an executable image onto the multi-processor system. At each step, checks may be performed for possible optimizations, and one or more steps repeated using results of the checks.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: September 12, 2023
    Assignee: Coherent Logix, Incorporated
    Inventors: Michael L. Purnell, Geoffrey N. Ellis, Teng-I Wang
  • Patent number: 11757962
    Abstract: A system and method for wirelessly transmitting audiovisual information. A first plurality of packets including audiovisual information may be generated. A second plurality of packets including error correction coding information for the audiovisual information may be generated. Control information for associating the error correction coding information with the audiovisual information may be generated, and a third plurality of packets including the control information may also be generated. The plurality of packets, including the first, second, and third pluralities of packets, may be transmitted to a mobile device in a wireless manner. The control information may inform the mobile device of the association of the first error correction coding information with the audiovisual information.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: September 12, 2023
    Assignee: Coherent Logix, Incorporated
    Inventors: Kevin A. Shelby, Peter J. Nysen, Michael B. Doerr
  • Patent number: 11726812
    Abstract: A multiprocessor system and method for swapping applications executing on the multiprocessor system are disclosed. The plurality of applications may include a first application and a plurality of other applications. The first application may be dynamically swapped with a second application. The swapping may be performed without stopping the plurality of other applications. The plurality of other applications may continue to execute during the swapping to perform a real-time operation and process real-time data. After the swapping, the plurality of other applications may continue to execute with the second application, and at least a subset of the plurality of other applications may communicate with the second application to perform the real time operation and process the real time data.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: August 15, 2023
    Assignee: Coherent Logix, Incorporated
    Inventors: Wilbur William Kaku, Michael Lyle Purnell, Geoffrey Neil Ellis, John Mark Beardslee, Zhong Qing Shang, Teng-I Wang, Stephen E. Lim
  • Patent number: 11720479
    Abstract: System and method for testing a device under test (DUT) that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: August 8, 2023
    Assignee: Coherent Logix, Incorporated
    Inventors: Geoffrey N. Ellis, John Mark Beardslee, Michael B. Doerr, Ivan Aguayo, Brian A. Dalio
  • Patent number: 11706641
    Abstract: Techniques for operating a wireless network in a plurality of radio operating environments are disclosed. In some embodiments, an apparatus receives a first parameter value set that is selected from a group of multiple parameter value sets, wherein the first parameter value set is appropriate for a first target radio operating environment that corresponds to one or more of: a first level of mobility of user devices or a first range of wireless transmission. In some embodiments, the apparatus is reconfigured to receive wireless broadcast transmissions from a second broadcast transmitter using a second parameter value set that is appropriate for a second target radio operating environment. The first and second broadcast transmitters may be the same or different. The parameter value sets may include a first parameter based upon which the apparatus is configured to determine subcarrier spacing and a second parameter that indicates a cyclic prefix size.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: July 18, 2023
    Assignee: Coherent Logix, Incorporated
    Inventors: Tommy K. Eng, Kevin A. Shelby
  • Patent number: 11689215
    Abstract: Wireless transport of multiple service versions of a transport framework. First and second information may be processed for transmission, respectively, according to first and second service versions of a transport framework. The first and second information may be encoded using a first type of error correction coding; after processing, the processed first information may include error correction coding according to the first type of error correction coding, while the processed second information may remain uncoded according to the first type of error correction coding. Control information may be generated indicating that the second information remains uncoded according to the first type of error correction coding, which may signal to receivers that the second information is processed according to the second service version of the transport framework.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: June 27, 2023
    Assignee: Coherent Logix, Incorporated
    Inventors: Kevin A. Shelby, Peter J. Nysen, Michael B. Doerr
  • Patent number: 11683860
    Abstract: Methods and devices for a home power networking system including a first wireless access point (AP) configured to perform wired communications over a first circuit connected to the first wireless AP. The first wireless AP further performs wireless communications with a second wireless AP, wherein the second wireless access point is connected to a second circuit and is not connected to the first circuit. The first wireless AP provides wireless transport through the second wireless AP to bridge communications between the first circuit and the second circuit.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: June 20, 2023
    Assignee: Coherent Logix, Incorporated
    Inventors: Kevin A. Shelby, Michael B. Doerr, Michael B. Solka, Yama Yasha
  • Patent number: 11677437
    Abstract: Methods and devices for dynamically designated first and second subsets of a plurality of frequency channels as upstream and downstream channels, respectively, for performing wired communications using virtual segmentation between a network controller and an endpoint device. performing virtual segmentation to service an endpoint device. Communications are performed between the network controller and the endpoint device through a wired communication medium using the upstream and downstream channels. The first subset and second subsets of the plurality of channels are designated as upstream channels and downstream channels, respectively, based at least in part on one or both of upstream and downstream channel demand and channel availability.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: June 13, 2023
    Assignee: Coherent Logix, Incorporated
    Inventors: Kevin A. Shelby, Michael B. Doerr
  • Patent number: 11671642
    Abstract: Control information for configuring an audiovisual device to present multimedia content according to a first service type may be generated. A method may include generating first control information for configuring an audiovisual device to decode a multimedia stream, generating first data that indicates a structure of the first control information, and transmitting the first data and the first control information. The first control information may be generated according to a first protocol version. Second data and second control information may be similarly generated and transmitted according to a second protocol version. Disclosed techniques may facilitate receiving devices to determine whether they support received wireless transmissions and decode the transmissions based on the control information.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: June 6, 2023
    Assignee: Coherent Logix, Incorporated
    Inventors: Colleen J. McGinn, Kevin A. Shelby, Peter J. Nysen, Michael B. Doerr
  • Patent number: 11594301
    Abstract: System and method for constructing a hierarchical index table usable for matching a search sequence to reference data. The index table may be constructed to contain entries associated with an exhaustive list of all subsequences of a given length, wherein each entry contains the number and locations of matches of each subsequence in the reference data. The hierarchical index table may be constructed in an iterative manner, wherein entries for each lengthened subsequence are selectively and iteratively constructed based on the number of matches being greater than each of a set of respective thresholds. The hierarchical index table may be used to search for matches between a search sequence and reference data, and to perform misfit identification and characterization upon each respective candidate match.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: February 28, 2023
    Assignee: Coherent Logix, Incorporated
    Inventors: Michael B. Doerr, Jan D. Garmany, Stephen V. Wood, Daemon G. Anastas, Martin A. Hunt
  • Patent number: 11550750
    Abstract: A multi-processor system with processing elements, interspersed memory, and primary and secondary interconnection networks optimized for high performance and low power dissipation is disclosed. In the secondary network multiple message routing nodes are arranged in an interspersed fashion with multiple processors. A given message routing node may receive messages from other message nodes, and relay the received messages to destination message routing nodes using relative offsets included in the messages. The relative offset may specify a number of message nodes from the message node that originated a message to a destination message node.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: January 10, 2023
    Assignee: Coherent Logix, Incorporated
    Inventors: Carl S. Dobbs, Keith M. Bindloss, Kenneth R. Faulkner, Alex E. Icaza, Frederick A. Rush, Faisal A. Syed, Michael R. Trocino
  • Patent number: 11483580
    Abstract: A split architecture for encoding a video stream. A source encoder may encode a video content stream to obtain an encoded bitstream and a side information stream. The side information stream includes information characterizing rate and/or distortion estimation functions per block of the video content stream. Also, a different set of estimation functions may be included per coding mode. The encoded bitstream and side information stream may be received by a video transcoder, which transcodes the encoded bitstream to a client-requested picture resolution, according to a client-requested video format and bit rate. The side information stream allows the transcoder to efficiently and compactly perform rate control for its output bitstream, which is transmitted to the client device. This split architecture may be especially useful to operators of content delivery networks.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: October 25, 2022
    Assignee: Coherent Logix, Incorporated
    Inventors: Michael W. Bruns, Michael B. Solka, Carl S. Dobbs, Martin A. Hunt, Michael B. Doerr, Tommy K. Eng
  • Patent number: 11405245
    Abstract: Methods and devices are described for polar encoding and decoding control information that has been modulated based on one or more identifiers of the transmitter and/or receiver. Some embodiments describe scrambling sequence design for multi-mode block discrimination on control information blind detection and decoding. Separate scrambling masks may be applied to disparate bit fields within a coded DCI message, wherein each of the scrambling masks is derived from a user equipment (UE)-specific identifier, a UE group identifier, or a base station identifier. Frozen bits of the polar code may be used to encode and transmit hybrid automatic repeat request (HARQ) acknowledgment messaging for early retransmission of unsuccessful downlink messages. A tiered process of UE identification may be employed to improve a balance between early termination of the decoding process and success of the UE identification process.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: August 2, 2022
    Assignee: Coherent Logix, Incorporated
    Inventors: Kevin A. Shelby, Feng Liu, David R. Starks, Mark Earnshaw
  • Patent number: 11356200
    Abstract: Methods and devices are described for determining reliabilities of bit positions in a bit sequence for information bit allocation using polar codes. The reliabilities are calculated using a weighted summation over a binary expansion of each bit position, wherein the summation is weighted by an exponential factor that is selected based at least in part on the coding rate of the polar code. Information bits and frozen bits are allocated to the bit positions based on the determined reliabilities, and data is polar encoded as the information bits. The polar encoded data is then transmitted to a remote device.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: June 7, 2022
    Assignee: Coherent Logix, Incorporated
    Inventor: Kevin A. Shelby