Patents Assigned to Coherent Logix, Incorporated
  • Patent number: 10185608
    Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: January 22, 2019
    Assignee: Coherent Logix, Incorporated
    Inventors: Carl S. Dobbs, Michael R. Trocino, Michael B. Solka
  • Patent number: 10185672
    Abstract: Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: January 22, 2019
    Assignee: Coherent Logix, Incorporated
    Inventors: Carl S. Dobbs, Michael R. Trocino
  • Patent number: 10129601
    Abstract: Techniques are disclosed relating to spectrum sharing between different radio access technologies. In some embodiments, a broadcast base station is configured to wirelessly broadcast audio and video data to a plurality of broadcast receiver devices using a particular frequency band. In these embodiments, the broadcast base station is configured to discontinue broadcasting in the particular frequency band during a scheduled time interval, to enable one or more cellular base stations to perform bi-directional packet-switched wireless data communications using the particular frequency band.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: November 13, 2018
    Assignee: Coherent Logix, Incorporated
    Inventors: Kevin A. Shelby, Durga P. Prasad, Sandeep Mavuduru Kannappa, Mark Earnshaw
  • Patent number: 10114739
    Abstract: System and method for testing a DUT that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: October 30, 2018
    Assignee: Coherent Logix, Incorporated
    Inventors: Geoffrey N. Ellis, John Mark Beardslee, Michael B. Doerr, Ivan Aguayo, Brian A. Dalio
  • Patent number: 10110345
    Abstract: Various embodiments are described of a system and method for improved SCL decoder operation. In particular, various embodiments are described which improve the efficiency of the buffer management based on updated path metric statistics. In some embodiments, the SCL decoder may perform selective replacement to limit the extent of LLR updates per row only to the statistics that have changed since the previous update cycle. In some embodiments, the SCL decoder may perform deferred updates, which may involves in-place calculation of both û?=0 and û?=1 bit estimate (LLR) updates based on the row from which the updated row will be derived.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: October 23, 2018
    Assignee: Coherent Logix, Incorporated
    Inventors: Zahir Raza, Kevin A. Shelby
  • Patent number: 10075857
    Abstract: Techniques for operating a wireless network in a plurality of radio operating environments are disclosed. In some embodiments, an apparatus receives a first parameter value set that is selected from a group of multiple parameter value sets, wherein the first parameter value set is appropriate for a first target radio operating environment that corresponds to one or more of: a first level of mobility of user devices or a first range of wireless transmission. In some embodiments, the apparatus is reconfigured to receive wireless broadcast transmissions from a second broadcast transmitter using a second parameter value set that is appropriate for a second target radio operating environment. The first and second broadcast transmitters may be the same or different. The parameter value sets may include a first parameter based upon which the apparatus is configured to determine subcarrier spacing and a second parameter that indicates a cyclic prefix size.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: September 11, 2018
    Assignee: Coherent Logix, Incorporated
    Inventors: Tommy K. Eng, Kevin A. Shelby
  • Patent number: 10033566
    Abstract: Techniques are disclosed relating to generating and receiving radio frames with multiple portions that have different encoding schemes. An apparatus may include one or more processing elements configured to receive, via a wireless radio, wireless data that includes a plurality of portions that each include multiple orthogonal frequency-division multiplexing (OFDM) symbols. Different ones of the portions have different frequency transform sizes and different sampling rates. The wireless data may also include control data that indicates the frequency transform sizes and sampling rates for the ones of the portions. The apparatus may select, based on the control data and a determined velocity of the apparatus, one or more but not all of the plurality of portions and may decode the selected one or more portions to determine data represented by the OFDM symbols in the selected one or more portions. Different portions of the wireless data may be adapted for decoding by devices moving at different maximum velocities.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: July 24, 2018
    Assignees: Coherent Logix, Incorporated, Sinclair Television Group, Inc.
    Inventors: Michael J. Simon, Kevin A. Shelby, Mark Earnshaw
  • Patent number: 10034147
    Abstract: In a next generation broadcast architecture, a broadcast gateway may send segments of a data file to a broadcast transmission system and to a server. The broadcast transmission system wirelessly transmits the segments to a user equipment (UE) device. When the UE device fails to decode a segment, it sends a request for re-transmission of the segment to the server via an IP network. The server re-transmits the requested segment to the UE device via the IP network. Furthermore, the gateway may receive one or more IP data flows (e.g., video streams) having variable bit rate. The gateway may apply dynamically-variable coding to the IP data flows so that the resulting coded IP data flows have an aggregate bit rate that matches a constant physical transport rate of the broadcast transmission system.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: July 24, 2018
    Assignees: Coherent Logix, Incorporated, Sinclair Television Group, Inc.
    Inventors: Kevin A. Shelby, Michael J. Simon
  • Patent number: 10007806
    Abstract: Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: June 26, 2018
    Assignee: Coherent Logix, Incorporated
    Inventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, David A. Gibson
  • Patent number: 10007293
    Abstract: Embodiments of a synchronous digital system are disclosed that may include generation of clock and synchronization signals. Any of a plurality of available clock signals may be selected for use as a primary clock, without causing clock-induced errors in the synchronous digital system. A clock signal generated on-chip with the synchronous digital system may be automatically selected in response to detecting a condition indicating that use of a local clock may be necessary. Such conditions may include detection of tampering with the synchronous digital system. If an indication of tampering is detected, security measures may be performed.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: June 26, 2018
    Assignee: Coherent Logix, Incorporated
    Inventors: Carl S. Dobbs, Michael R. Trocino, Kenneth R. Faulkner, Christopher L. Schreppel
  • Patent number: 9990227
    Abstract: A multiprocessor system and method for swapping applications executing on the multiprocessor system are disclosed. The plurality of applications may include a first application and a plurality of other applications. The first application may be dynamically swapped with a second application. The swapping may be performed without stopping the plurality of other applications. The plurality of other applications may continue to execute during the swapping to perform a real-time operation and process real-time data. After the swapping, the plurality of other applications may continue to execute with the second application, and at least a subset of the plurality of other applications may communicate with the second application to perform the real time operation and process the real time data.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: June 5, 2018
    Assignee: Coherent Logix, Incorporated
    Inventors: Wilbur William Kaku, Michael Lyle Purnell, Geoffrey Neil Ellis, John Mark Beardslee, Zhong Qing Shang, Teng-I Wang, Stephen E. Lim
  • Patent number: 9990241
    Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: June 5, 2018
    Assignee: Coherent Logix, Incorporated
    Inventors: Carl S. Dobbs, Michael R. Trocino, Michael B. Solka
  • Patent number: 9973301
    Abstract: Various embodiments are described of a system and method for improved SCL decoder operation. In particular, various embodiments are described which improve the efficiency of the buffer management based on updated path metric statistics. In some embodiments, the SCL decoder may perform selective replacement to limit the extent of LLR updates per row only to the statistics that have changed since the previous update cycle. In some embodiments, the SCL decoder may perform deferred updates, which may involves in-place calculation of both û?=0 and û?=1 bit estimate (LLR) updates based on the row from which the updated row will be derived.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: May 15, 2018
    Assignee: Coherent Logix, Incorporated
    Inventors: Zahir Raza, Kevin A. Shelby
  • Patent number: 9965258
    Abstract: A computer-implemented method for creating a program for a multi-processor system comprising a plurality of interspersed processors and memories. A user may specify or create source code using a programming language. The source code specifies a plurality of tasks and communication of data among the plurality of tasks. However, the source code may not (and preferably is not required to) 1) explicitly specify which physical processor will execute each task and 2) explicitly specify which communication mechanism to use among the plurality of tasks. The method then creates machine language instructions based on the source code, wherein the machine language instructions are designed to execute on the plurality of processors. Creation of the machine language instructions comprises assigning tasks for execution on respective processors and selecting communication mechanisms between the processors based on location of the respective processors and required data communication to satisfy system requirements.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: May 8, 2018
    Assignee: Coherent Logix, Incorporated
    Inventors: John Mark Beardslee, Michael B. Doerr, Tommy K. Eng
  • Patent number: 9960787
    Abstract: Wireless transport of multiple service versions of a transport framework. First and second information may be processed for transmission, respectively, according to first and second service versions of a transport framework. The first and second information may be encoded using a first type of error correction coding; after processing, the processed first information may include error correction coding according to the first type of error correction coding, while the processed second information may remain uncoded according to the first type of error correction coding. Control information may be generated indicating that the second information remains uncoded according to the first type of error correction coding, which may signal to receivers that the second information is processed according to the second service version of the transport framework.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: May 1, 2018
    Assignee: Coherent Logix, Incorporated
    Inventors: Kevin A. Shelby, Peter J. Nysen, Michael B. Doerr
  • Patent number: 9913153
    Abstract: Techniques for operating a wireless network in a plurality of radio operating environments are disclosed. In some embodiments, an apparatus receives a first parameter value set that is selected from a group of multiple parameter value sets, wherein the first parameter value set is appropriate for a first target radio operating environment that corresponds to one or more of: a first level of mobility of user devices or a first range of wireless transmission. In some embodiments, the apparatus is reconfigured to receive wireless broadcast transmissions from a second broadcast transmitter using a second parameter value set that is appropriate for a second target radio operating environment. The first and second broadcast transmitters may be the same or different. The parameter value sets may include a first parameter based upon which the apparatus is configured to determine subcarrier spacing and a second parameter that indicates a cyclic prefix size.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: March 6, 2018
    Assignee: Coherent Logix, Incorporated
    Inventors: Tommy K. Eng, Kevin A. Shelby
  • Patent number: 9904542
    Abstract: Techniques for specifying and implementing a software application targeted for execution on a multiprocessor array (MPA). The MPA may include a plurality of processing elements, supporting memory, and a high bandwidth interconnection network (IN), communicatively coupling the plurality of processing elements and supporting memory. In one embodiment, software code may include first program instructions executable to perform a function. In this embodiment, the software code may also include one or more language constructs that are configurable to specify one or more communication ports and one or more parameter inputs. In this embodiment, the one or more communication ports are configurable to specify communication with other software code. In this embodiment, the one or more parameter inputs are configurable to specify a set of hardware resources usable to execute the software code. In this embodiment, the hardware resources include multiple processors and may include multiple supporting memories.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: February 27, 2018
    Assignee: Coherent Logix, Incorporated
    Inventors: Stephen E. Lim, Viet N. Ngo, Jeffrey M. Nicholson, John Mark Beardslee, Teng-I Wang, Zhong Qing Shang, Michael Lyle Purnell
  • Patent number: 9900364
    Abstract: A system and method for wirelessly transmitting audiovisual information. A first plurality of packets including audiovisual information may be generated. A second plurality of packets including error correction coding information for the audiovisual information may be generated. Control information for associating the error correction coding information with the audiovisual information may be generated, and a third plurality of packets including the control information may also be generated. The plurality of packets, including the first, second, and third pluralities of packets, may be transmitted to a mobile device in a wireless manner. The control information may inform the mobile device of the association of the first error correction coding information with the audiovisual information.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: February 20, 2018
    Assignee: Coherent Logix, Incorporated
    Inventors: Kevin A. Shelby, Peter J. Nysen, Michael B. Doerr
  • Patent number: 9749879
    Abstract: A method for operating a wireless network in a plurality of radio operating environments is disclosed. A first parameter value set is selected from a library of two or more parameter value sets. Each of the parameter value sets includes a value for each of one or more communication-related parameters. The first parameter value set is appropriate for a first target radio operating environment. The action of selecting the first parameter value set is performed for a first set of one or more infrastructure radios that are to be operated in the first target radio operating environment. The first parameter value set is applied to the first set of one or more infrastructure radios so that the first set of one or more infrastructure radios will start using the first parameter value set to wirelessly communicate with user devices.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: August 29, 2017
    Assignee: COHERENT LOGIX, INCORPORATED
    Inventors: Tommy K. Eng, Kevin A. Shelby
  • Patent number: 9720867
    Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: August 1, 2017
    Assignee: COHERENT LOGIX, INCORPORATED
    Inventors: Carl S. Dobbs, Michael R. Trocino, Michael B. Solka