Abstract: A process for forming, on a semiconductor substrate, an isolation structure between two zones of an integrated circuit wherein active regions of electronic components integrated thereto have already been defined, comprises the steps of:defining an isolation region on a layer of silicon oxide overlying a silicon layer;selectively etching the silicon to provide the isolation region;growing thermal oxide over the interior surfaces of the isolation structure;depositing dielectric conformingly; andoxidizing the deposited dielectric.

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided.

Abstract: A high-frequency bipolar transistor structure includes a base region of a first conductivity type formed in a silicon layer of a second conductivity type, the base region comprising an intrinsic base region surrounded by an extrinsic base region, an emitter region of the second conductivity type formed inside the intrinsic base region, the extrinsic base region and the emitter region being contacted by a first polysilicon layer and a second polysilicon layer respectively. The first and the second polysilicon layers are respectively contacted by a base metal electrode and an emitter metal electrode. Between the extrinsic base region and the first polysilicon layer, a silicide layer is provided to reduce the extrinsic base resistance of the bipolar transistor.

Abstract: A low offset amplifier has an output stage constituted by an npn transistor and a pnp transistor in a push-pull arrangement, and a driver stage. The latter includes a current-mirror circuit having, in its input branch, a pnp transistor in series with a first constant-current generator and, in its output branch, an npn transistor, and two complementary bipolar transistors with collectors connected together to the output terminal and the bases are connected together to the input terminal of the amplifier. The emitter of the pnp transistor of the driver stage is connected to the positive terminal of the supply by a second constant-current generator and to the base of the npn transistor of the output stage, and the emitter of the npn transistor of the driver stage is connected to the negative terminal of the supply by the npn transistor of the output branch of the current-mirror circuit and to the base of the pnp transistor of the output stage. The amplifier has a very low or zero offset (Vos=Vout-Vin).

Abstract: The invention relates to a voltage regulator connected between first and second voltage references and having an output terminal for delivering a regulated output voltage. The voltage regulator includes at least one voltage divider, connected between the output terminal and the second voltage reference, and a serial output element connected between the output terminal and the first voltage reference. The voltage divider is connected to the serial output element by a first conduction path which includes at least one error amplifier whose output is connected to at least one driver for turning off the serial output element. The voltage regulator includes, between the voltage divider and the serial output element, at least a second conduction path for turning off the serial output element according to a value of the regulated output voltage in advance of the action of the first conduction path.

Abstract: Memory and storage method in an electronic controller operating with fuzzy logic procedures for membership functions (FA) of logical variables (M) defined in a so-called discourse universe (U) discretized at a finite number of points (m) which provide memorization of triangular or trapezoid membership functions (FA). Memory words have a first portion for codification of the vertex of the membership function (FA), a second portion for a codification corresponding to the slope of one side of the membership function (FA), and a third portion for a codification corresponding to the slope of the other side of the function.

Abstract: There is described a bipolar power transistor with high breakdown voltage, obtained in a heavily doped semiconductor substrate of the N type, over which a lightly doped N type layer, constituting a collector region of the transistor, is superimposed. The transistor has a base region comprising a heavily doped P type diffusion, which extends into the lightly doped N type layer from a top surface. The transistor further includes an emitter region constituted by a heavily doped N type diffusion extending from the top surface within said heavily doped P type diffusion. The heavily doped P type diffusion is obtained within a deep lightly doped P type diffusion, extending from said top surface into the lightly doped N type layer and formed with acceptor impurities of aluminum atoms.

Abstract: A zero thermal budget manufacturing process for a MOS-technology power device.

Abstract: A method for storing a membership function, include storing a position of a vertex of a triangle that defines the membership function in a universe of discourse and storing a first distance between the position of the vertex a point of intersection between a left side of the triangle and an axis of the universe of discourse. Further, the method includes storing a second distance between the position of the vertex and point of intersection between right side of the triangle and the axis of the universe of discourse. The present invention furthermore relates to a circuit for calculating a grade of membership of an antecedent of a fuzzy rule, and is adapted to fuzzyfy an input variable by adopting the geometric proportions that occur between homologous sides of similar triangles defined by the position of the input value in the universe of discourse.

Abstract: A current-controlled multivibrator having increased accuracy independent of variations in process and temperature. The oscillator employs a bandgap voltage in combination with a current generator to ensure operational stability despite temperature and process variations.

Abstract: A power semiconductor structure (200), in particular in VIPower technology, made from a chip of N-type semiconductor material (110), comprising a bipolar or field-effect vertical power transistor (125, 120, 110) having a collector or drain region in such N-type material (110); the semiconductor structure comprises a PNP bipolar lateral power transistor (210, 110, 220) having a base region in such N-type material (110) substantially in common with the collector or drain region of the vertical power transistor.

Abstract: A MOS-gated power device includes a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value. Under each body region a respective lightly doped region of the second conductivity type is provided having a second resistivity value higher than the first resistivity value.

Abstract: A method and apparatus for the localized reduction of the lifetime of charge carriers in integrated electronic devices. The method comprises the step of implanting ions, at a high dosage and at a high energy level, of a noble gas, preferably helium, in the active regions of the integrated device so that the ions form bubbles in the active regions. A further thermal treatment is performed after the formation of bubbles of the noble gas in order to improve the structure of the bubbles and to make the noble gas evaporate, leaving cavities in the active regions.

Abstract: An integrated edge structure for a high voltage semiconductor device comprising a PN junction represented by a diffused region of a first conductivity type extending from a semiconductor device top surface is described. The edge structure comprises a first, lightly doped ring of the first conductivity type obtained in a first, lightly doped epitaxial layer of a second conductivity type and surrounding said diffused region, and a second, lightly doped ring of the first conductivity type, comprising at least one portion superimposed on and merged with said first ring, obtained in a second, lightly doped epitaxial layer of the second conductivity type grown over the first epitaxial layer.

Abstract: A process for manufacturing an integrated structure pad assembly for wire bonding to a power semiconductor device chip including a chip portion having a top surface covered by a metallization layer which has a first sub-portion wherein functionally active elements of the power device are present. The chip portion has at least one second sub-portion wherein no functionally active elements of the power device are present. The top surface of the at least one second sub-portion is elevated with respect to the first sub-portion to form at least one protrusion which forms a support surface for a wire.

Abstract: The device presents a polysilicon layer extending over a wafer of semiconductor material, along the edge of the active region of the device, and partly over a thick field oxide layer which externally delimits the active region. The polysilicon layer forms both a field-plate region at its inner edge, and a Zener protection diode over the field oxide layer, outwards of and contiguous to the field-plate region. The terminals of the diode are respectively connected to the source metal region and the gate metal region; the diode therefore extends along the whole of the perimeter of the device, and presents an extensive junction area without greatly reducing the active area of the device.

Abstract: A high-speed MOS-technology power device integrated structure includes a plurality of elementary functional units formed in a lightly doped semiconductor layer of a first conductivity type, the elementary functional units including channel regions of a second conductivity type covered by a conductive insulated gate layer including a polysilicon layer; the conductive insulated gate layer also including a highly conductive layer superimposed over the polysilicon layer and having a resistivity much lower than the resistivity of the polysilicon layer, so that a resistance introduced by the polysilicon layer is shunted with a resistance introduced by the highly conductive layer and the overall resistivity of the conductive insulated gate layer is lowered.

Abstract: A voltage booster circuit including a pull-up capacitor connected to the supply line via a PMOS switching transistor. The other terminal of the pull-up capacitor is supplied with a pull-up voltage switching between a first value determining charging of the capacitor, and a second value higher than the first and determining pull-up of the capacitor. A negative voltage source presents an output connected to the control terminal of a switch transistor, and generates a negative voltage of a value lower than the first pull-up voltage value when charging the capacitor, so as to saturate the switch transistor and charge the capacitor to a voltage close to the supply voltage.

Abstract: A method for storing a membership function, include storing a position of a vertex of a triangle that defines the membership function in a universe of discourse and storing a first distance between the position of the vertex a point of intersection between a left side of the triangle and an axis of the universe of discourse. Further, the method includes storing a second distance between the position of the vertex and point of intersection between right side of the triangle and the axis of the universe of discourse. The present invention furthermore relates to a circuit for calculating a grade of membership of an antecedent of a fuzzy rule, and is adapted to fuzzify an input variable by adopting the geometric proportions that occur between homologous sides of similar triangles defined by the position of the input value in the universe of discourse.

Abstract: A MOS-technology power device including a semiconductor material layer of a first conductivity type having a body region disposed therein. The body region includes a heavily doped region of a second conductivity type, a lightly doped region of the second conductivity type and a heavily doped region of the first conductivity type and a process of making same. A method of making the semiconductor device includes forming an insulated gate layer on portions of the surface of the semiconductor material layer to leave selected portions of the semiconductor material layer exposed. Ions of the second conductivity type are implanted into the selected regions of the semiconductor material layer. The implanted ions are thermally diffused to form body regions, each body region including a heavily doped region substantially aligned with the edges of the insulated gate layer, and a lightly doped region formed by lateral diffusion of the first dopant under the insulated gate layer.