Abstract: Method and apparatus of parallel processing of multiple inference rules organized in fuzzy sets or logical functions of multiple fuzzy sets including membership functions defined in a so-called universe of discourse. The inference rules are configured essentially as IF-THEN rules with at least one antecedent preposition and at least one consequent implication. The prepositions have at least one term of comparison between membership functions and a plurality of input data and each term is separated by logical operators. The method associates with the logical operators maximum and minimum operations among two or more elements and calculates exhaustively the overall degree of truth (.OMEGA.) of a rule with a maximum or minimum of N partial truth levels. The method is accomplished by a plurality of identical, parallel inferential processors. Each inferential processor determines a preposition or a partial truth level of a preposition.

Abstract: A semiconductor device including a substrate having a first conductivity type on which are formed first and second epitaxial layers of the same conductivity type of the substrate. The semiconductor device also includes a first diffused region having a second conductivity type formed in a first portion of the first and second epitaxial layers. Said first diffused region defines a first junction with said first and second epitaxial layers. The semiconductor device also comprises an edge structure having the second conductivity type formed in a second portion of the first and second epitaxial layers. The edge structure includes a second diffused region having the second conductivity type formed in the first and second epitaxial layers, said second diffused region defining a second junction with said first and second epitaxial layers.

Abstract: A high-frequency lateral PNP transistor includes a base region laterally delimited by P type emitter and collector regions, and at the top by a surface portion of the N type semiconductor body housing the active area of the transistor. The surface portion delimiting the base region presents no formations of insulating material grown across the surface, so that the width (W.sub.B) of the base region is reduced and ensures optimum dynamic characteristics of the transistor. The base contact may be located directly over the surface portion facing the base region, to reduce the extrinsic base resistance and overall size of the device, or it may be located remotely and connected to the base region by a buried layer and sinker region to further reduce the base width.

Abstract: An integrated structure active clamp for the protection of a power device against overvoltages includes a plurality of serially connected diodes, each having a first and a second electrode, obtained in a lightly doped epitaxial layer of a first conductivity type in which the power device is also obtained; a first diode of said plurality of diodes has the first electrode connected to a gate layer of the power device and the second electrode connected to the second electrode of at least one second diode of the plurality whose first electrode is connected to a drain region of the power device; said first diode has its first electrode comprising a heavily doped contact region of the first conductivity type included in a lightly doped epitaxial layer region of the first conductivity type which is isolated from said lightly doped epitaxial layer by a buried region of a second conductivity type and by a heavily doped annular region of the second conductivity type extending from a semiconductor top surface to said bu

Abstract: Disclosed is a bonding pad for a semiconductor chip which prevents damage during a bonding process. In a semiconductor chip having conductive regions interconnected by a metal pattern, a metal region is disposed over the metal pattern. The metal region forms a bonding pad area over the conductive regions. In addition, the metal region is in direct contact with the metal pattern for substantially the whole bonding pad area. With this arrangement, the metal region absorbs mechanical stress induced when a bonding wire is bonded to the metal region during a bonding process. The metal region is sufficiently thick so as not to be perforated during the bonding process and the metal pattern is, therefore, not damaged.

Abstract: A process for making a package for discrete semiconductor devices, wherein the insulating characteristics of the package are increased by introducing cuts, grooves and positioning holes in the metal plate and shaping in the retractable positioning pins of the metal plate in the molding die.

Abstract: A circuit for protecting from overload currents includes an electronic power device having at least first and second terminals and at least one control terminal. The circuit also includes at least one voltage-generating circuit for generating a reference voltage having a predetermined pattern. The voltage-generating circuit includes at least a first terminal connected to the first terminal of the power device and at least a second terminal coupled to the second terminal of the power device through a sensor. The circuit also preferably includes at least one comparator for comparing the reference voltage with a voltage present across the sensor. The comparator has at least one output terminal and at least first and second input terminals. The first and second input terminals are respectively connected to a third terminal of the voltage-generating circuit and the second terminal of the power device.

Abstract: A method for detecting an open load includes the use of a driver having at least one main power transistor connected to the load and one auxiliary transistor connected in parallel with the main transistor between a first power supply voltage reference and a second voltage reference. The method compares a first voltage present on a terminal connected to the load of the main transistor with a second voltage present on a terminal of the auxiliary transistor. A circuit for detecting an open load performs the method.

Abstract: A pulse generator has an input and two outputs at which to respectively generate pulses in relation to different types of signal edges received at the input of the generator. The generator provides two distinct logic circuit blocks of the sequential type, the blocks being mutually independent for generation of the pulses at the two outputs. In this manner it is possible to easily control the characteristics of the pulses. In addition, if two blocks are connected with appropriate and simple logic networks, it is possible in the generation phase to impose conditions between the pulses at the two outputs in a simple manner and with a certain freedom.

Abstract: A circuit for generating a reference voltage and detecting a drop in a supply voltage, comprising at least one threshold comparator having an input terminal and an output terminal, and a voltage divider connected between a first supply voltage reference and a second voltage reference and connected to the input terminal of the comparator, further provides for the output terminal of said comparator to be connected to the input terminal through at least one feedback network comprising at least one current generator. The feedback network further comprises a buffer block having an input terminal connected to said comparator and a first output terminal connected to a switch which is connected between a circuit node of said voltage divider and the second voltage reference.

Abstract: A differential charge pump circuit employing a lowpass filter network which is chargeable and dischargeable by switchingly controlled current generators. The differential charge pump employs two identical current generators for injecting the same current I in a substantially continuous manner, on the two significant nodes of the lowpass filter. The differential charge pump also employs two pairs of identical, switchingly controlled current generators connected to the two significant nodes, respectively, each capable of pulling a current I. The two generators forming each of the two pairs of switchingly controlled current generators are controlled by one of a pair of control signals (UP, DOWN) and by the inverted signal of the other of the pair of control signals, respectively. All four switchingly controlled generators may be of the same type (N-type), thus ensuring high speed and precision.

Abstract: A circuit for use with an ignition system to enable detection of an overvoltage condition in the primary winding of an ignition coil caused by opening of a power switch connected to the primary winding. The circuit senses the overvoltage condition by comparing the voltage on the primary winding to a first threshold voltage and produces a signal at an output terminal indicative of the presence of the overvoltage condition. The output terminal is maintained at a high logic level upon detection of an overvoltage condition and throughout the time duration of the overvoltage condition, and drops to a low logic level when the voltage on the primary winding falls to a second threshold voltage, which is lower than the first threshold voltage. Comparison circuitry is provided for sensing the overvoltage condition by reference to fixed voltage values. Logic circuitry responds to the comparison circuitry to produce the appropriate logic levels at the output terminal.

Abstract: A method and apparatus for forming buried oxide layers within silicon wafers comprising several steps. Recesses are formed in a silicon wafer. Light ions are implanted in the silicon wafer at a depth that is smaller than the depth of the recesses to form bubbles of the light ions in the silicon wafer. The light ions are evaporated from the silicon wafer to leave cavities in the place of the bubbles. The cavities are oxidized through the recesses to form a buried layer of silicon oxide.

Abstract: An analog multiplier includes at least a differential output stage formed by a pair of emitter-coupled bipolar transistors. Each transistor of the pair of emitter-coupled bipolar transistors is driven by a predistortion stage having a reciprocal of a hyperbolic tangent transfer function that is attributable to the base currents of the bipolar transistors used in the predistortion stage. The error in the output signal produced by the analog multiplier is compensated by generating replicas of the base currents of the bipolar transistors of the differential output stage and forcing those replica currents on the output node of a respective predistortion stage. Various embodiments that consume different amounts of power are described.

Abstract: A method, and associated circuit, which can prevent the latch-down phenomenon in transistors which are protected from going out of their SOAs.By supplementing the first protection circuit (against moving out of the SOA) with a second protection circuit which can drive the control terminal of the transistor such that when, upon the voltage across the main conduction path of the transistor being increased, the value of the current flowing through said path would tend, due to the first protection, to drop below a predetermined lower limit, that value can be kept approximately constant and unaffected by the load as seen from the output terminal of the transistor; the transistor will at all events supply the load with some current up to the acceptable limit VMAX by the transistor.

Abstract: A start up circuit causes a MOS transistor to be turned on by sensing local electrical quantities thereof, specifically the potential at the drain terminal of the MOS transistor. A small current is injected into the control terminal of the MOS transistor when the potential at the drain terminal is high. For the purpose, an electric network is arranged to couple these two terminals together.

Abstract: A non-dissipative device for protecting an integrated circuit having multiple independent channels against overloading. The non-dissipative device includes an input terminal and an output terminal having an integrated switch connected therebetween which consists of an input portion, a logic gate with two inputs a control portion, and an output portion, all connected in series with one another. The device further includes a generating circuit for generating the on-times and off-times of the integrated switch, the generating circuit is connected between an output of the output portion and an input of the logic gate.

Abstract: A method and system for processing a plurality of fuzzy logic rules. The system includes a plurality of fuzzy logic lines, each fuzzy logic line corresponding to one of the fuzzy logic rules and including a calculating device. Each calculating device has an input terminal for receiving a series of weights and an output terminal for outputting an overall truth value according to the received series of weights and at least one logical operator of the fuzzy logic rule corresponding to the fuzzy logic line. The system further includes processing circuitry coupled to each fuzzy logic line, for receiving the overall truth value from each line, and outputting a fuzzy logic value according to the received overall truth values.

Abstract: The invention relates to a control circuit for semiconductor devices which is formed on a substrate (1) doped by a first dopant type, the integrated circuit comprising a first epitaxial layer (2) grown on the substrate (1) and doped by the first dopant type, and an isolation well (3) doped by a second dopant type, the control circuit comprising at least a first control transistor (M1) formed in a first well (8) doped by the second dopant type and formed in the insulation well (3). Thus, the control circuit comprises at least one N-channel MOS transistor accommodated within a well in direct contact with the isolation well to eliminate a buried layer that, in prior art arrangements, involved the presence of an undesired parasitic component.

Abstract: A PIC structure includes a lightly doped semiconductor layer of the first conductivity type superimposed over a heavily doped semiconductor substrate of a second conductivity type, wherein a Vertical IGBT and a driving and control circuit including at least first conductivity type-channel MOSFETs are integrated. The MOSFETs are provided inside well regions of the second conductivity type which are included in at least one lightly doped region of the first conductivity type completely surrounded and isolated from the lightly doped layer of the first conductivity type by means of a respective isolated region of a second conductivity type.