Abstract: The disclosure describes a current feedback amplifier that contains an additional pair of emitter follower transistors connected between inputs of current mirrors, with a capacitor connected to the common emitters of the emitter follower transistors to reduce discontinuities in the output current provided from the current mirrors. The capacitor is used to turn on the non-dominant current mirror prior to the time it is required to dominate the output. In this manner, glitches introduced due to delays in a current mirror switching from an off state to an on state are significantly reduced.

Abstract: A delay circuit is provided for use in a ring oscillator of a phase locked loop (PLL). The delay circuit includes a differential pair of NMOS transistors 102 and 103 with an NMOS transistor 101 providing the tail current for the differential pair. Complementary NMOS and PMOS load transistors 104,106 and 105, 107 provide loads for the differential transistor 102 and 103. Transistors 111-114 and 121-122 together with an amplifier 130 provide biasing for the delay device. The amplifier 130 has a non-inverting input set to VDD−VCLAMP. As configured, a constant output voltage swing from VDD to VDD−VCLAMP is provided at the outputs VOUT+ and VOUT− of the delay device, independent of a control voltage VCTL used to set the tail current. The NMOS load transistor 104, as opposed to the PMOS transistor 4 in FIG. 1, does not contribute to the gate parasitic capacitance enabling a high operation speed without consumption of more supply current.

Abstract: An improved amplifier includes an input stage differential amplifier (100) with an output forming a gain node (102), an output stage buffer (104) having an input connected to the gain node (102), a compensation capacitor (106) connected from the gain node (102) to ground, and a correction amplifier (200) with a first input connected to the output of the output stage buffer (104), a second input connected to the input of the output stage buffer (104), and having an output connected to the gain node (102), the correction amplifier further including a correction capacitor (304) connected between the input and output of the output stage buffer (104). The correction capacitor (304) preferably has a capacitance value (C′) set equal to the capacitance (Ccomp) of the compensation capacitor (106).

Abstract: A method for forming a semiconductor substrate is provided including the general sequential steps of: providing a handle wafer and a device wafer; implanting at least a first impurity region in a first surface of the device wafer; bonding the first surface of the device wafer to a first surface of the handle wafer having a silicon dioxide layer; removing a portion of the device wafer at a second surface; and forming an epitaxial silicon layer on the second surface of the device wafer. The process enables the thickness of the device wafer to be minimal.

Abstract: An intermediate stage for a rail-to-rail input/output CMOS opamp includes a floating current source separating two current mirrors (151-154,155-158), where the ideal current source includes a floating current mirror (500,501,502,503,504,505) enabling an output quiescent current to be provided which does not vary with changes in the voltage rails or the common-mode input voltage, and enabling elimination of input offset caused by the mismatch of the two current sources (164,166). The NMOS transistor (502) has a source-drain path provided in series with a PMOS transistor (505) serving to connect the current mirrors (151-154) and (155-158) and to eliminate input offset.

Abstract: An intermediate stage for a rail-to-rail input/output CMOS opamp includes a floating current source separating two current mirrors (151-154,155-158), where the ideal current source includes a floating current mirror (500,501,502,503,504,505) enabling an output quiescent current to be provided which does not vary with changes in the voltage rails or the common-mode input voltage, and enabling elimination of input offset caused by the mismatch of the two current sources (164,166). The NMOS transistor (502) has a source-drain path provided in series with a PMOS transistor (505) serving to connect the current mirrors (151-154) and (155-158) and to eliminate input offset.

Abstract: An offset error voltage cancellation circuit which may be used with a folded cascode amplifier. The folded cascode amplifier includes a differential amplifier having transistors (100) and (102) with collectors connected to a resistor (110) having a value (R1) and a resistor (112) having a value (R2), and transistors (120) and (122) for folding back current having emitters connected to the resistors (110) and (112). The error cancellation circuit includes resistors (210) and (212) having values (R1′) and (R2′) matching the respective values (R1) and (R2), along with cross coupled transistors (220) and (222) connecting the resistors (210) and (212) to the emitters of transistors (120) and (122). As connected, the cross coupled transistors (220) and (222) and resistors (210) and (212) effectively form a negative resistance −(R1+R2) to cancel error voltage between the emitters of transistors (120) and (122).

Abstract: Control circuitry is used to provide a uniform temperature distribution between multiple power supplies on a chip which drive a single load. The power supplies each include a MOSFET with a source to drain path connecting VDD to the single load. The control circuitry includes a bipolar diode placed close to the MOSFET in each power supply unit, each diode providing a voltage varying inversely proportional to temperature changes resulting from power dissipated by its respective MOSFET. The control circuitry further includes components in each power supply unit to provide the voltage from the bipolar diode with the lowest voltage (or highest temperature) on a bus external to the power supply units. The bus voltage is then examined in the control circuitry in each of the power supply units and if the bipolar diode voltage in a unit is equal to the bus voltage, that unit does not increase current from its respective MOSFET to the load since it has the highest temperature.

Abstract: A method of forming a semiconductor substrate, comprising the steps of: providing a device substrate of a first conductivity type having a first surface and a second surface, and a handle substrate; depositing a dopant in the first surface of the wafer; diffusing the dopant through the wafer from the first surface toward the second surface, thereby forming a well; bonding the first surface of the device wafer to the handle substrate; and thinning the device substrate to yield a final device layer with a retrograde well. The dopant may be of the first or a second conductivity type.

Abstract: A method for dissipating accumulated charge in a trench isolation structure, comprising the steps of: etching the trench region into a silicon substrate; forming an insulating region on the sidewalls of the trench and the base of the trench; removing the insulator at the bottom of the trench; and filling the trench with polysilicon, the polysilicon engaging the second layer of silicon below the insulator layer.

Abstract: A method for dissipating accumulated charge in a trench isolation structure, comprising the steps of: forming a contact region of an area having a cross section greater than the width of the isolation structure; and coupling the isolation structure to a charge dissipation means.

Abstract: The present invention is a differential amplifier with circuitry to eliminate the effect of transistor impedance other than an actual load impedance on voltage gain. The circuitry includes a pair of transistors 400 and 402, each with a base connected to a respective input of the differential amplifier along with a similar base connection of a respective one of transistors 100 and 102, and an emitter connected to a current source 404. A collector of transistor 400 is connected through transistor 410 to the emitter of a current sink transistor 306, while the collector of transistor 402 is connected through transistor 412 to the emitter of a current sink transistor 308. Operational amplifiers (opamps) 420 and 422 serve as voltage followers to connect the collector of transistor 100 to the base of transistor 412, and the collector of transistor 102 to the base of transistor 410.

Abstract: A silicon on insulator (SOI) process is disclosed which includes the steps of forming an etch stop layer in a starting wafer, forming an insulating layer on the etch stop layer, bonding this wafer to a handle wafer, thinning the start wafer down to the etch stop and then recovering a device layer from the etch stop layer by outgassing dopants from the etch stop layer.

Abstract: A circuit for generating an output signal used for driving a grounded load is provided. The circuit provides an output signal without glitches or spikes. The circuit also outputs a drive signal with enhanced responsiveness in transitioning from one output value level to another output value level. The circuit includes a plurality of control devices for providing respective output signals responsive to respective control signals. The base of a PNP transistor is coupled to the output of the control devices and acts as a buffer. The emitter of the PNP transistor is coupled to a voltage source and the collector is coupled to a grounded load for providing the drive current. Alternatively, an NPN transistor and current source provides the drive current to the grounded load. The circuitry may be used in an optical disk drive with the load and ground being a laser diode used for providing a laser beam in reading/writing an optical disk.

Abstract: A variable frequency oscillator providing a constant amplitude with variations in frequency. The variable frequency oscillator includes: an oscillator having an input connected for receiving a current I.sub.1, and outputs for providing complementary signals having a frequency varying in proportion to the current I.sub.1 ; first and second transistors, each having a base connected to a respective one of the oscillator outputs; current supply circuitry having a first output connected to the input of the oscillator for providing the current I.sub.1, and a second output connected to the emitters of the first and second transistors for providing a current I.sub.3, the current I.sub.3 varying in proportion to the current I.sub.

Abstract: A video sync slicing circuit is disclosed that employs an adjustable gain control (AGC) amplifier and circuitry that adjusts a gain of the AGC amplifier such that a blanking level of the video signal at an output of the AGC amplifier equals a blanking reference voltage. The slicing circuit includes a circuit that triggers a composite sync signal when a sync pulse of the video signal equals the fifty percent slicing level.

Abstract: A liquid etch apparatus including an outer tank for holding a liquid etch solution, which has included therein an inner cylindrical member positioned in the outer tank. At one end of the inner cylindrical member, a sparger or other gas supply means may be provided. Filters are provided between the inner cylindrical member and the outer tank. Substrates are secured in the inner tank and a propeller is provided below the substrates. Gas is introduced into the inner cylindrical member during the etch process which creates a pressure gradient between the inner tank and the outer tank, forcing particulate matter carried by the gaseous particles to circulate around to the filters.

Abstract: A circuit used with a differential amplifier to eliminate the effect of Early Voltage from voltage gain provided by the differential amplifier. With a differential amplifier utilizing PNP transistors which experience the lowest, and most undesirable Early Voltage, the circuitry includes a pair of transistors 400 and 402, each with a base connected to an input of the differential amplifier corresponding to a similar base connection of a respective one of transistors 100 and 102 of the differential amplifier, an emitter connected to a current source, and a collector connected to the collector of a respective one of NPN current sink transistors 306 and 308 connected at outputs of the differential amplifier. The circuitry for elimination of Early Voltage further includes components to assure the collector voltages of transistors 400 and 402 are equal and the collector voltages of transistors 102 and 400 are equal.

Abstract: An integrated circuit chip with multiple switching element segments that cooperatively provide high power switching is provided with circuitry for isolating each individual switching element segment. The individual isolation of switching element segments enables bond wire continuity testing.

Abstract: A monolithic power control circuit is disclosed that includes a switching element and a control circuit that senses a voltage drop across the switching element and that adjusts a duty cycle of the switching element. The monolithic circuit includes a compensation circuit that adjusts a contribution of the sensed voltage drop across the switching element in response to temperature changes of the switching element.