Abstract: A polishing tool having a polishing wheel that forms a set of pockets wherein the pockets receive a stream of water and are formed such that a high hydrostatic pressure builds in the pockets as the polishing tool rotates in a high precision grinding machine and addresses a surface of a substrate. The high hydrostatic pressure removes material from the surface of the substrate while preserving the precise thickness variation control of the high precision grinding machine.

Abstract: A semiconductor wafer in an intermediate stage of fabrication having an array of slices. All but one of the slices may have integrated circuit components interconnected by metallization layers to form a die having an operable circuit, with the remaining slice functioning as a scribe area or line. Two embodiments of slices are disclosed in which one slice is a rectangle of a minimum width to function as a scribe area, and the other slice is composed of a sliver and a rectangle with the latter also having a minimum width to function as a scribe area. Each embodiment of a slice can be extended lengthwise with an extension box that also can function to contain operative components or function as a scribe area.

Abstract: An amplifier includes an output buffer having an input coupled to a gain node which is the common node of the outputs of first and second current mirrors for receiving a signal current and having an output for providing an amplified drive current. The output buffer includes a first transistor of a first type having its base coupled to a gain node of the output buffer and to the base of a first transistor of a second type for receiving the signal current. The emitter of the first transistor of a first type is coupled to the base of a second transistor of a second type. The emitter of the first transistor of the second type is coupled to the base of a second transistor of the first type. The emitter of the second transistor of the first type is coupled to the emitter of the second transistor of the second type and to the output of the buffer.

Abstract: A current feedback amplifier having circuitry in its input stage for matching the error current created due to a parasitic capacitance (C.sub.IN) on the negative, or inverting input terminal (V.sub.IN-). Additional circuitry in the input stage subtracts the matching current from the error current created by C.sub.IN to cancel the error current due to C.sub.IN and thus eliminate the peaking of gain at high frequencies caused by C.sub.IN. In addition to cancellation of C.sub.IN errors, the subtraction process in the input stage enables cancellation of error current resulting from bias current common mode rejection (ICMR) as well as component dissimilarities created during processing.

Abstract: A capacitance compensation circuit for a current feedback amplifier which compensates for error current created due to a parasitic capacitance C.sub.IN on the negative, or inverting input terminal V.sub.IN. The capacitance compensation circuit includes a capacitor C* connected to the positive input terminal V.sub.IN+ utilized to couple current from V.sub.IN+ to the collectors of emitter follower transistors having bases coupled to V.sub.IN+ and emitters connected to V.sub.IN-.

Abstract: An amplifier circuit is disclosed having circuitry that senses an electrical current at the output node while dynamically adjusting a bias current for an output circuit of the amplifier circuit. The bias current controls the amount of electrical current that the output circuit sinks or sources at the output node.

Abstract: An integrated active filter and sync separator circuit operates on precision internal reference sources to set the filter cut off frequency as a function of resistance of an external resistor. The active filter eliminates the source of sync tip crushing attributable to conventional clamping circuits associated with sync pulse detectors, and also provides sync pulses substantially devoid of time-variant jitter.

Abstract: An amplifier has an output buffer having an input coupled to the second outputs of the first and second current mirrors for receiving the biasing current and having an output for providing an amplified drive current. The output buffer includes a first transistor of a first type having its base coupled to the input of the output buffer and to the base of a first transistor of a second type. The emitter of the first transistor of a first type coupled to the base of a second transistor of a second type, and a collector. The emitter of the first transistor of the second type is coupled to the base of a second transistor of the first type. The emitter of the second transistor of the first type is coupled to the emitter of the second transistor of the second type and to the output of the buffer. First and second current mirrors of complementary transistor types provide a reference current and a biasing current in response to a programming current and a feedback current.

Abstract: A class AB complementary output stage provides maximum output voltage swings and high load currents with minimum power dissipation. The output stage includes a first bias circuit that generates a pair of voltage nodes with a resistor controlled bias current. A second bias circuit comprises four current sources the outputs of which are coupled pair-wise across a resistor to form a pair of high impedance nodes at the resistor terminals. The voltage nodes of the first bias circuit establish bias currents in a differential input stage and in a pair of current sources of the second bias circuit. The outputs of the differential input stage drive the inputs of second pair of current sources in the second bias circuit, which provide drive current to the high impedance nodes. The output circuit comprises a pair of complementary common source transistors, the gates (bases) of which are driven by the high impedance nodes of the second bias circuit.

Abstract: A voltage controlled amplifier which includes a gain core and a transconductive amplifier. The gain core includes two complimentary differential transistor pairs. The emitters of the four transistors of the two differential pairs are connected to complimentary diode connected transistors. The diode connected transistors balance the parasitic resistances of the dissimilar transistors, thereby, reducing differential gain and distortion.

Abstract: An active folded cascode includes an amplifier transistor and a source follower transistor configured as a folded cascode with the drain of the amplifier transistor and the source of the follower transistor connected to form a gain node. A feedback transistor has its gate and drain connected to the source and gate of the follower transistor while bias current provided to the drain of the feedback transistor by a current source maintains the gain node at a fixed voltage with respect to a reference voltage. Coupling of the voltage at the gain node to the gate of the source follower transistor by the feedback transistor reduces the effective source impedance of the source follower transistor, providing improved gain and bandwidth properties for the active folded cascode circuit.

Abstract: A differential analog memory cell provides output signals governed by precisely adjustable voltage levels having minimal drift. The memory cell comprises a pair of differentially connected floating gate MOSFETs, each MOSFET having its source connected to a common current source and its drain connected to one leg of a current mirror. The floating gate of each MOSFET is connected to one electrode of a tunneling capacitor and one electrode of a coupling capacitor. Voltages applied to the other electrode of the tunneling capacitor inject charges onto the corresponding floating gate, the voltage of which is determined by the size of the coupling capacitor. Output voltages taken from the drains of the floating gate MOSFETs can be precisely adjusted up or down by applying single polarity voltage pulses to one or the other injector nodes.

Abstract: A multiplexer circuit includes pairs of control elements such as CMOS transistors serially connected between common circuit nodes to conduct current therebetween in response to one of each pair of control elements being selectively biased to conductive or non-conductive states by an applied control signal. The current enabled to flow between circuit nodes through a pair of control elements biased to conductive state is determined by the magnitude of an applied signal, and a current-difference circuit compares the current flowing between circuit nodes with a reference current to produce an output signal representative of the applied signal which is selected in response to an applied control signal.

Abstract: A scheme is presented for offsetting varactor error currents that are coupled to the gain nodes of amplifier circuits through transistors having their collectors connected to these gain nodes. For each vatactor error current generating transistor, a compensating diode circuit is connected so as to replicate the vatactor error current, and the replicated current is coupled to the gain node to offset the vatactor error current of the corresponding transistor. In order to replicate the vatactor error current of a given transistor, each compensating diode circuit comprises a diode for which the capacitance and the voltage dependence thereof substantially track those of the collector-base junction of the corresponding transistor. The voltage driving the vatactor error current in the transistor is coupled to one electrode of the compensating diode, the other electrode of which is connected to the emitter of the transistor having its collector connected to the gain node.

Abstract: A current feedback amplifier having circuitry in its input stage for matching the error current created due to a parasitic capacitance (C.sub.IN) on the negative, or inverting input terminal (V.sub.IN-). Additional circuitry in the input stage subtracts the matching current from the error current created by C.sub.IN to cancel the error current due to C.sub.IN and thus eliminate the peaking of gain at high frequencies caused by C.sub.IN. In addition to cancellation of C.sub.IN errors, the subtraction process in the input stage enables cancellation of error current resulting from bias current common mode rejection (ICMR) as well as component dissimilarities created during processing.

Abstract: A four quadrant multiplier comprises X and Y input stages for coupling signals to a gain core amplifier for multiplication, wherein each of the input stages and the gain core amplifier further comprises a pair of complementary circuits, based on devices having opposite conductivity properties. The complementary X-input stage is a dual differential amplifier which provides balanced, differential outputs when loaded by the gain core differential amplifiers, due to separate cancellation of the npn and pnp base currents within the loaded X-input stage. Outputs from the cross-connected gain core amplifiers provide a pair of complete, ground referenced product signals having opposite phases. The X-input stage is also suitable for driving other complementary, differential stages such as two quadrant multipliers, voltage controlled amplifiers, and high speed analog multiplexing circuits.

Abstract: A low power complementary gain control circuit adjusts the gain of an input signal with a gain control signal to provide a ground referenced output signal having low distortion. The gain control circuit includes an input stage having the topology of a current feedback amplifier input stage, which operates in conjunction with a complementary pair of gain control amplifiers and a complementary pair of current mirrors to control the amplitude of an input signal by means of a control signal applied to the gain control amplifiers. Each gain control amplifier comprises a pair of differentially connected transistors of the same conductivity type, the common emitters, the collectors, and the bases of the differentially connected transistors forming the current input, current outputs, and gain control inputs of the gain control amplifier.

Abstract: An amplifier stage suitable for current conveyors and current mode feedback operational amplifiers has low input resistance and operates at low power. The amplifier stage comprises a buffer having inverting and non-inverting inputs and a pair of current outputs, and a pair of multiple output current mirrors which operate in conjunction with the buffer to generate an output current at a high gain node in response to an input signal applied to the buffer inputs. Each multiple output current mirror has a low impedance current input for receiving current signals generated by the buffer and multiple high impedance current outputs for providing current feedback to the inverting input of the buffer and output current to the high gain node of the amplifier stage. The magnitudes of the feedback and output currents are determined by the resistances of current scaling resistors associated with the low impedance current input and each of the high impedance current outputs.

Abstract: An analog multiplier includes a plurality of input stages that are selectively coupled to inputs of a common amplifier through coupling elements and logic circuitry that selectively controls conduction through the coupling elements to the amplifier. The coupling elements include transistors that are common base connected to a bias supply for shunting capacitive feed through to the amplifier.

Abstract: A current feedback operational amplifier input stage is provided that uses a pair of dual output current mirrors to couple current from the inverting input of the amplifier to the high gain node of the amplifier, and to reduce the input impedance of the inverting input by means of local current feedback. Each of the dual output current mirrors employs an emitter degenerated Wilson-type current mirror in conjunction with an emitter degenerated transistor current source to detect signal current at the inverting input and use this current to control the bias current at both the inverting input and the high impedance node of the amplifier. The ratio of bias currents in the dual output current mirrors are controlled by scaling the resistances of the emitter degeneration resistors corresponding to each current node.