Abstract: An input termination circuit with high impedance at power off, which includes a first transistor coupled between a first terminal and a second terminal. The input termination circuit also includes a control circuit that monitors voltages on the first and second terminals and a first voltage source. During power off conditions, the control circuit couples the gate of the first transistor to a voltage that will keep the first transistor off. The first transistor remains off even when the voltage levels at the first and second terminals vary wildly.

Abstract: A circuit for putting an output driver into a high impedance state upon failure of the power supply. This is accomplished by providing a first transistor that is connected between the power supply and the n-well to charge the n-well node of the PMOS drive transistor. Upon failure of the supply voltage, a number of transistors are connected to couple the n-well and a gate of the PMOS drive transistor to the output line, so that they track the voltage level of the output, thereby preventing forward biasing of the P+/n-well diode.

Abstract: A method and circuitry for implementing programmable gain. More particularly, embodiments of the present invention provide an amplifier circuit which can be used as a CDS-amp or an instrumentation amplifier. Included is a two-stage amplifier, each stage having a few as one transistor. A current source biases one stage of the two-stage amplifier. A load resistor network couples to the two-stage amplifier and is configured to set gain values for the two-stage amplifier.

Abstract: A circuit for putting an output driver into a high impedance state upon failure of the power supply. This is accomplished by providing a first transistor that is connected between the power supply and the n-well to charge the n-well node of the PMOS drive transistor. Upon failure of the supply voltage, a number of transistors are connected to couple the n-well and a gate of the PMOS drive transistor to the output line, so that they track the voltage level of the output, thereby preventing forward biasing of the P+/n-well diode.

Abstract: A rectifier circuit with a transistor having first and second electrodes coupled between an input and output of the rectifier circuit. A latch has an output connected to a control node of the transistor, and has first and second inputs connected to the input and output of the rectifier circuit, respectively. The invention provides a self-contained, self-powered, self-regulated low turn-on voltage diode-rectifier with maximum current (on-state conductance) when forward-biased. This circuit can be inserted between any two nodes and behaves like a Schottky diode.

Abstract: A method and circuitry for implementing low-power analog-to-digital converters. More particularly, embodiments of the present invention provide an amplifier circuit for pipeline ADCs having multiple stages, some in sample mode, some in hold mode. The stages include residue amplifiers which include a pre-amp and a current source. The current source is turned off during the sample mode. Some embodiments include a second current source that provides a bleeder current during the sample phase so that the pre-amp remains in steady state.

Abstract: A programmable fuse structure using an MOS transistor. A voltage potential is switched across the gate of the MOS transistor, with the gate resistance causing it to heat the MOS structure. This causes a short at one or more of a number of locations in the MOS structure, thereby programming the MOS transistor. A programming circuit with the MOS transistor in a feedback path is provided. This feedback provides a self-timing feature, such that immediately after the fuse is programmed, its programming operation ceases.

Abstract: A method and apparatus for automatically determining the protocol being used from the frequency of an applied clock without the need for a separate pin or switch or a second external clock. The clock's frequency is identified when its frequency falls into the set range for which the apparatus is targeted. Based on the detected frequency in the set range, a mode select signal is generated. The mode select signal causes the chip to configure to the appropriate frequency for that mode, as well as any other unique configuration parameters. In one embodiment, the invention generates a ramp signal triggered by the external clock (which is the clock frequency for the desired protocol). The clock is simultaneously applied to a counter. When the ramp signal reaches a reference voltage, the count of the counter is compared to at least one threshold to determine to which frequency it corresponds. In response to this determination, the chip is configured according to the communication mode or protocol indicated.

Abstract: A method and apparatus for automatically determining the protocol being used from the frequency of an applied clock without the need for a separate pin or switch or a second external clock. The clock's frequency is identified when its frequency falls into the set range for which the apparatus is targeted. Based on the detected frequency in the set range, a mode select signal is generated. The mode select signal causes the chip to configure to the appropriate frequency for that mode, as well as any other unique configuration parameters. In one embodiment, the invention generates a ramp signal triggered by the external clock (which is the clock frequency for the desired protocol). The clock is simultaneously applied to a counter. When the ramp signal reaches a reference voltage, the count of the counter is compared to at least one threshold to determine to which frequency it corresponds. In response to this determination, the chip is configured according to the communication mode or protocol indicated.

Abstract: A digital LBO in which digitized versions of the desired waveforms are stored in memory. A selection circuit allows the selection of certain ones of said waveforms corresponding to an anticipated amount of signal degradation over a transmission line. A digital-to-analog converter converts those certain waveforms into analog waveforms for transmission.

Abstract: A programmable delay in an AFE of an imaging system which can vary both the pulse position and the pulse width. The pulse width and position are controlled by providing separate programmable delay circuits for the rising and falling edges of the desired timing signal. Combining logic then combines the outputs of the two delay circuits to produce an output clock with separately delayed rising and falling edges.

Abstract: The present invention provides an ESD structure that can tolerate voltages at the I/O pin, or pad, higher than the voltage allowed for such technology. More particularly, the present invention provides an electrostatic discharge integrated circuit having a first and second NMOS transistor, a first and second voltage divider, a first and second steady state biasing circuit. The first NMOS transistor sinks electrostatic discharge current from an input/output pad to a ground source, the first NMOS transistor having a drain coupled to the input/output pad, and a gate. The first voltage divider has a node connected to the gate of the first NMOS transistor. The first steady state biasing circuit connects to the gate of the first NMOS transistor. The second NMOS transistor sinks electrostatic discharge current from the input/output pad to the ground source, the second NMOS transistor having a drain coupled to a source of the first NMOS transistor, and a source coupled to the ground source.

Abstract: An indirect current sensing circuit and method for replicating an output current is disclosed. The present invention is capable of preventing device damage and circuit disruption by maintaining output voltage signal integrity and consuming negligible power as well as optimizing output impedance. Furthermore, the indirect current sensing circuit and method is independent of semiconductor process variations and thus is more reliable over prior art current sensing techniques. The indirect current sensing circuit and its method of current limiting and output impedance optimization, according to the present invention, can reliably drive transmission lines in networking system and communication applications.

Abstract: The present invention provides a short circuit power limiter circuit having a current sensor and a power limiter. The short circuit sensor sends a short circuit flag signal to the power limiter when the short circuit sensor detects a short circuit condition in a target circuit. The power limiter then reduces the power consumption of the target circuit. In a specific example, the power limiter toggles a particular portion of the target circuit on and off to reduce the circuit's average short circuit power consumption. This cycle is repeated as long as a short circuit condition exists.

Abstract: A simple, cost-effective compression circuit which compress raw color data without interpolation. Control points common to all the colors in a line are generated each time one of the colors exceeds the color change threshold. The change in the other color is recorded at the same time even though it doesn't exceed the minimum change threshold.

Abstract: A clock recovery circuit which has a transition detector connected to the incoming data stream. An output of the transition detector is connected to a gate, such as a D flip-flop, which has an input receiving the recovered clock. A zero or one output will be generated depending upon whether the transition is before or after the rising edge of the recovered clock. An accumulator circuit accumulates a count for each transition, providing the results to a comparison circuit. The comparison circuit compares the accumulated count to maximum and minimum thresholds, and provides advance or retard outputs when those thresholds are exceeded. A phase circuit adjusts the phase of the recovered clock by advancing or retarding it after a sufficient number of transitions have been detected either in advance or behind the recovered clock to justify such an adjustment.

Abstract: The present invention provides an integrated circuit driver having multiple resistance paths that switch on at different stages of the rising and falling transitions of the driver's output signal waveform. The driver also has a control circuit configured to turn on the one or more resistance paths during at least one predetermined stage of the output signal during transitions, thus reducing the control circuit's effective resistance to control the slope of the transitions during the predetermined stage.

Abstract: An image sensor integrated circuit with a pixel cell having photogates wherein each photogate has a number of gaps which allow light to penetrate to the substrate. The gaps are open in the direction of the floating diffusion, in order to minimize the trapping of charges. In a preferred embodiment, the floating gate has a comb structure, with the tines of the comb extending toward the floating gate. Preferably, the tines or fingers are wider than the gaps. In a preferred embodiment, the gaps are no wider than 3 microns.

Abstract: A phase detector which detects the phase difference between the input clock and an output clock. That phase difference is used to gate a high frequency clock, which is provided to the clock input of an up/down counter. The phase detector also indicates whether the phase difference is positive or negative. When the counter reaches a pre-specified up or down count, an advance or retard signal is provided to a phase selector. The phase selector selects one of multiple phases of a clock used for the output clock.

Abstract: An analog-to-digital converter which has a low resolution and high resolution mode. In response to the low resolution mode signal, a switching circuit selects only certain of the digital bit outputs. In one embodiment, the analog-to-digital converter is a pipelined circuit with a number of stages. In response to the low resolution mode, a number of the stages are bypassed, so that only the needed stages for the smaller number of bits are used. The stages that are bypassed are preferably powered down, but not completely. By maintaining a small amount of bias current to the bypassed stages, they can quickly respond when a switch is made back to full resolution mode.