Abstract: A system includes a first switch connected to a voltage input and a switching node. A second switch is connected to the switching node and a reference potential. A first circuit generates first rising edges and first falling edges by comparing a voltage at the switching node to a first voltage reference. The first voltage reference is between the reference potential and the voltage input. A second circuit generates second rising edges and second falling edges by comparing the switching node voltage to a second voltage reference. The second voltage reference is less than the reference potential. The controller calculates delay times based on the first rising edges, the first falling edges, the second rising edges and the second falling edges. The controller generates drive signals for the first switch and the second switch based on a duty cycle and the delay times.

Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented.

Abstract: A folder common cascode circuit with symmetric parallel signal paths from the differential inputs to the differential outputs provides a low skew, low jitter, low power differential amplifier. The signal paths on either side of the differential amplifier are made equal with equal loads along each path. Pairs of complementary NMOS and PMOS transistor pairs with parallel complementary biasing stacks on the output cascode circuitry maintain symmetrical parallel signal paths, amplification and impedance loading from differential input to differential output. Output voltage translating inverters provide a higher voltage level output signal while maintaining low skew and jitter.

Abstract: A die attach package for connecting a die or chip of die-down orientation to a printed circuit board in a die-up orientation. The package includes a substrate with leads that may be traces terminating in vias or that may be the leads of a lead frame. The traces or the leads of the lead frame are modified such that they pass under the die when the die is attached. The traces or leads are routed under the die such that proper connections are established from the topside of the die to the appropriate mount locations of the printed circuit board. The die is attached to the substrate using a non-electrically-conductive material. This packaging enables a fabricator to make die of one orientation type, die down, and use that die in a die-up package, thereby saving on fabrication costs.

Abstract: An overvoltage protection circuit arranged to sense removal of the overvoltage condition. The protection circuit blocks current passing through a pull up transistor of an output circuit to a high-potential supply rail during an overvoltage condition applied at a common bus. The protection circuit includes one protection branch controlled by the potential at the bus and powered by the high-potential supply rail of the output circuit to be protected. The protection circuit also includes a second protection branch controlled by the high-potential supply rail and powered by the potential on the bus. When an overvoltage condition occurs, the second branch is activated and regulates an output from the first protection branch. That output signal controls the control node of the pull up transistor of the output circuit to be protected.

Abstract: A method of forming an improved Schottky diode structure as part of an integrated circuit fabrication process that includes the introduction of a selectable concentration of dopant into the surface of an epitaxial layer so as to form a barrier-modifying surface dopant layer. The epitaxial layer forms the cathode of the Schottky diode and a metal-silicide layer on the surface of the epitaxial layer forms the diode junction. The surface dopant layer positioned between the cathode and the diode junction is designed to raise or lower the barrier height between those two regions either to reduce the threshold turn-on potential of the diode, or to reduce the reverse leakage current of the transistor. The particular dopant conductivity used to form the surface dopant layer is dependent upon the conductivity of the epitaxial layer and the type of metal used to form the metal-silicide junction.

Abstract: A high-frequency switch circuit having an MOS pass gate or transfer transistor. The switch circuit of the invention includes a first impedance element coupled to the gate of the transfer transistor and, preferably, an alternative second impedance element coupled to the bulk of the transfer transistor. One or both of the impedance elements substantially negates the low-parasitic shunt capacitance associated with the transfer transistor that controls signal attenuation under high frequency operation. The impedance element is coupled in series with that parasitic capacitance to increase substantially the impedance of that pathway, thereby increasing substantially the passable bandwidth. The impedance element may simply be a resistor. The switch circuit is suitable for use in an array of applications, including signal propagation in computing systems, routers, and flat panel screen displays.

Abstract: A CMOS-based circuit for translating a differential-input into a single-ended output capable of driving large loads with little or no compromise in speed. This translator provides a symmetric single-ended output signal capable of driving a wide range of loads with minimal distortion. In contrast to earlier such translators, the circuit of the present invention ensures that the output signal is coupled directly to the high-voltage rail after being switched to logic HIGH and that that coupling remains in effect until an input signal causing the output to switch to logic LOW is received. Similarly, when the output signal is switched to logic LOW, it is coupled directly to the low-voltage rail of the circuit and left so coupled until it is affirmatively switched to logic HIGH. This feature ensures that regardless of load, the output signal completely switches to the proper logic stage.

Abstract: A method for utilizing fractal analysis in the design and manufacture of semiconductor structures including transistor devices such as power MOS devices. The method includes using fractal theory to determine optimum source perimeter values to increase aspect ratio. The method is implemented to allow for use of the theoretical values in conjunction with known photolithographic fabrication techniques. The resultant structure thus incorporates the theoretically derived values to approximate a fractal structure.

Abstract: A buffer circuit for providing dynamic threshold control. The buffer circuit includes a pair of input inverters designed with different skewed threshold potential characteristics. The outputs of the skewed inverters are directed to a logic circuit designed to select either the faster or the slower signal received from the two inverters for transmission to passgate devices coupled to the respective inverters. Only one of the passgate devices is enabled to ensure that only one of the output signals from the two inverters is propagated through the buffer. A latch is preferably connected between the logic circuit and the two passgate devices to maintain the states of the inverters and the logic circuit. The circuit can be designed to define the threshold potential at which switching will occur so as to reduce propagation delay or increase it as desired. It is therefore possible using the circuit to increase transmission rates with minimal affect on signal noise.

Abstract: A logic level converter for translating CMOS logic signals to into differential logic signal pairs such as those associated with ECL levels. The converter includes a first converter branch coupled to the switchable CMOS level input and it provides a first switchable translated output. A second converter branch is not coupled to the input nor is it coupled to the first converter branch. The second converter branch provides a fixed reference signal output around which the output of the first converter branch switches. Changes in the input signal to the first converter branch cause its output potential to be more than or less than the potential of the fixed reference signal supplied by the second converter branch. The components of the respective branches may be tailored to position the fixed signal at a selectable level and to define the differential between the two output signals.

Abstract: A transfer gate or pass gate circuit for transferring logic signals between nodes for a range of available high-potential supply levels. The primary transfer gate is designed to protect against potentials that either exceed either a high-potential or a low-potential level or that undershoot such potential levels. For overshoot (overvoltage) tolerance, this is achieved by coupling a NMOS transistor in parallel with a pair of PMOS transistors that are coupled in series. All three transistors are located between two nodes, either of which can be the input or the output of the transfer gate. The NMOS transistor is designed to be larger than the PMOS transistors and carries most of the transfer capability. The smaller PMOS transistors are designed to eliminate potential drops that would otherwise occur with a single NMOS transistor or with a complementary pair of transistors.

Abstract: A CMOS-based bus-hold circuit having overvoltage tolerance. The bus-hold circuit of the present invention includes, in addition to conventional input and latching inverters, a sense circuit and an arbiter circuit designed in combination to block overvoltage events from powering the latching inverter. The sense circuit includes a comparator designed to compare the potential of a standard high-potential power supply rail to the potential associated with a signal applied to the bus-hold circuit's input node. The higher of those two potentials is used to activate the arbiter circuit that in turn couples the higher of those two signals to a pseudo high-potential power rail. The pseudo high-potential power rail is used to supply power to the latching inverter such that the latching inverter will not be activated during overvoltage conditions, particularly when the circuit is in its high-impedance state. The bus-hold circuit may be similarly designed to establish an undervoltage tolerance as well.

Abstract: A multiplexer for selecting a single output signal from a plurality of input signals. For a plurality of complementary input signal pairs in particular, the multiplexer includes for each pair of complementary input signals a control sub-circuit having a selection switch and a common resistance in parallel. The switch and the common resistance have a common low-potential node that is tied to a pair of resistances that are in parallel, wherein each of the parallel resistances is coupled to the respective high-potential nodes of a differential amplifier. A particular pair of incoming complementary input signal pairs controls the differential amplifier. An off-circuit selection signal selects which switch of a plurality of control sub-circuits is activated. When a switch is on, it creates a bypassing of the common resistance, thereby enabling the turn-on of output drivers coupled to the differential amplifier.

Abstract: A process for forming a trench in a semiconductor material is provided. The process includes (a) providing a semiconductor substrate, a first mask layer adjacent the surface of the semiconductor substrate, and a second mask layer adjacent the surface of the first mask layer, the second mask layer defining a first open area and the first mask layer defining a second open area that is larger than the first open area and aligned therewith in a manner so that in the area of the openings the first mask layer is undercut with respect to the second mask layer; and (b) removing a portion of the semiconductor substrate through the open area defined by the second mask layer to form a trench in said semiconductor substrate. An IC device formed using the process is also provided.

Abstract: An ESD protection device including a transistor structure with resistive regions located within active areas thereof. The transistor structure is formed of one or more MOS transistors, preferably N-type MOS transistors. The drain regions of the transistors are modified to reduce the conductivity of those resistive regions by preventing high carrier concentration implants in one or more sections of the drain regions. This is achieved by modifying an N LDD mask and the steps related thereto, as well as a silicide exclusion mask and the steps related thereto. The modifications result in the omission of N LDD dopant from the area immediately adjacent to the underlying channel. In addition, portions of a spacer oxide remain over the drain region to be formed. Subsequent implant and siliciding steps are effectively blocked by the spacer oxide that remains, leaving a low-density drain (LDD) charge carrier concentration in those regions, except where omitted.

Abstract: An accelerated endurance test structure and process that provides a wafer-level dielectric test. A wafer-level dielectric testing structure includes a heating element. The heating element may be poly-silicon or metal and is formed as a layer above a tunnel oxide layer of an integrated circuit (IC). A thermometer is provided to the heating element to regulate the temperature within the tunnel oxide area. The thermometer may be of a serpentine loop shape. Localized heating of the tunnel oxide structure occurs to a suitable temperature such as 250.degree. Celsius where the endurance test is accelerated so as to assure failure in as little as 10 seconds. Accelerated endurance data on the structure is modeled based on the Arrhenius Equation to accurately predict endurance of the devices contained on the IC.

Abstract: An output buffer for reducing the signal noise associated with the switching between logic high and logic low electrical. Signals includes a first clamping circuit linked to the pull-up output transistor of the buffer, and a second clamping circuit linked to the pull-down output transistor of the buffer. The buffer may include both clamping circuits or either the first or second clamping circuit alone, dependent upon signal shaping interests. Each of the clamping circuits includes a selectable delay stage coupled to the buffer's input, a current regulator controlled by the delay stage, and a clamping device that is coupled to the control node of the output transistor. When the current regulator is conducting, the control node of the output transistor is clamped at a potential near its threshold turn-on. As a result, when the clamping circuit is turned off, the output transistor experiences a soft turn-on, thereby reducing signal bounce and the associated noise.

Abstract: An additional isolation valve is incorporated into a vacuum processing system to increase the life of the system's mechanical pump, reduce maintenance costs and downtime, prevent particle back streaming and reduce safety risks to maintenance technicians. The system has a process chamber with at least one port, a foreline valve connected to the port, and a vacuum manifold in fluid communication with the foreline valve. The mechanical pump is connected to the vacuum manifold for evacuating the contents of the process chamber. The isolation valve is connected between the foreline valve and the vacuum manifold and is operated in unison, or primarily in unison, with the foreline valve.

Abstract: A dedicated hardware block in the form of a hardware bit coder device for generating IR/RF bit coding protocols. The hardware bit coder device is configurable to any user-defined frame length and single or multiple frame strings. The device can emulate substantially any desired bit coding pattern. The device uses a programmable signal shaping technique that eliminates the need to develop complex bit coding protocols in software. Using the hardware bit coder device of the present invention directly reduces the amount of program memory required by the microcontrollers to accomplish data decoding and also frees up the microcontroller resources for other purposes. The hardware bit coder includes a set of two pattern registers, one corresponding to a high data bit value and the other to a low data bit value. The particular pattern to be shifted out for transmission is defined by the particular data signal. Pattern transmission rate and period are selectable.