Patents Assigned to Fairchild Semiconductor Corporation
  • Semiconductor die package including low stress configuration
    Patent number: 9583454
    Abstract: A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: February 28, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Maria Clemens Y. Quinones, Maria Cristina B. Estacio
  • Apparatus and method for recovering from partial insertion of an audio jack
    Patent number: 9584893
    Abstract: Apparatus and methods for recovering from an audio jack connection anomaly such as a partial insertion of an audio jack plug with an audio jack receptacle are provided. In an example, a method can include detecting a valid audio jack connection of an audio jack receptacle and an audio jack plug, detecting a change in a state of a detect switch associated with the audio jack connection, applying an oscillating signal to a microphone terminal associated with the audio jack connection, determining the state of the detect switch stays constant for a predetermined time, and isolating the oscillating signal from the microphone terminal.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: February 28, 2017
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventor: John R. Turner
  • Dual-edge tracking synchronous rectifier control techniques for a resonant converter
    Patent number: 9584035
    Abstract: This disclosure provides control techniques for a resonant converter. In one control technique, for switching speeds that are below the resonant frequency of the primary stage of the converter, the switches of the synchronous rectifier (SR) portion (SR switches) of the resonant converter are controlled based on a rising edge of the corresponding primary side switch and the turn off time of a corresponding SR switch. In general, for below resonance operation, each corresponding SR switch will be turned off prior to the falling edge of each corresponding primary side switch, while each corresponding SR switch will be turned on at the rising edge of the each corresponding primary side switch. The conduction time of respective SR switches is generally constant for below resonance operation.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: February 28, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Hangseok Choi
  • Silicon carbide power bipolar devices with deep acceptor doping
    Patent number: 9577045
    Abstract: In a general aspect, a power semiconductor device can include a collector region disposed on a substrate, the collector region can include n-type silicon carbide (SiC). The power semiconductor device can also include a base region disposed on the collector region. The base region can include p-type SiC doped with gallium. The power semiconductor device can include an emitter region disposed on the base region. The emitter region can include n-type SiC carbide.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: February 21, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Andrei Konstantinov
  • Enhanced peak current mode DC-DC power converter
    Patent number: 9577519
    Abstract: Apparatus and methods are provided for feedback circuitry in a power converter, the feedback circuitry including a first resistor coupled to a first node between a high switch and a low switch, a first capacitor in series with the first resistor, the first capacitor coupled to a second node, a first comparator having a positive terminal connected between the first resistor and the first capacitor and a negative terminal connected to a third node, the first comparator configured to compare a voltage at the positive terminal to a voltage at the negative terminal, wherein the feedback circuitry is configured to generate a ramp waveform at the positive terminal of the first comparator, an amplitude of the ramp waveform based on a time constant of the first resistor and the first capacitor.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: February 21, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Edward P. Coleman
  • Combo ID detection
    Patent number: 9569388
    Abstract: This document discusses, among other things, an identification (ID) detection module configured to identify a first ID code in a first detect period within a first attach period and to identify a second ID code in a second detect period within the first attach period.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: February 14, 2017
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventor: Bert Marston
  • Ignition control circuit with dual (two-stage) clamp
    Patent number: 9559498
    Abstract: In a general aspect, an apparatus can include an insulated gate bipolar transistor (IGBT) device configured to control charging and discharging of an ignition coil and a two-stage voltage clamp coupled with the IGBT device. The two-stage voltage clamp can include a high-voltage portion coupled with the IGBT device and a low-voltage portion coupled with high-voltage portion and the IGBT device. The apparatus can further include a sense device coupled with the two-stage voltage clamp and a timing circuit coupled with the sense device. The timing circuit can be configured to provide a control signal to cause the sense device to enable or disable the high-voltage portion of the two-stage voltage clamp.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: January 31, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Scott Pearson
  • Circuit and method for overcurrent detection of power switch
    Patent number: 9551742
    Abstract: An overcurrent detection circuit for a power switch comprises a sampling circuit and a comparing circuit. The sampling circuit is configured to perform current sampling on the power switch using a sampling Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and an amplifier, convert a sample current into a sample voltage and transmit the sample voltage to the comparing circuit, and clamp operating voltages of the comparing circuit and of an output circuit of the amplifier by a serially connected clamping MOSFET. The comparing circuit is configured to compare the sample voltage with a reference voltage and to output a result of overcurrent detection.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: January 24, 2017
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventor: Lei Huang
  • Apparatus and method for operating and switching a single conductor interface
    Patent number: 9552317
    Abstract: This application discusses, among other things, communication apparatus and methods, and more particularly, a single conductor or single wire communication scheme. In an example, a method for communicating between a master device and a slave device using a first single conductor can include transmitting a first ping on the first single conductor using a master device, the first single conductor configured to couple the master device to a slave device, receiving a slave ping on the first single conductor at the master device during a ping interval, toggling a logic level of the first single conductor prior to sending a first data packet using pulses having a duration of less than one half of a unit interval, such as a unit interval associated with a bit interval.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: January 24, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Erik Maier, John R. Turner
  • System for battery management and protection
    Patent number: 9548604
    Abstract: The present disclosure is directed to a system for battery management and protection. A battery protection circuit may include a power semiconductor switch and a control integrated circuit (IC). The battery protection circuit may be configured to regulate the charging and/or discharging of a battery and further prevent the battery from operating outside of a safe operating area based on a protection trip point (e.g. overcurrent detection point) of the protection IC. The protection IC may be configured to calibrate a protection trip point so as to compensate for process and temperature variations of on resistance (RSSon) of the power semiconductor switch.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: January 17, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Tomas Andres Moreno, Joseph D. Montalbo, Sung Geun Yoon, Roger Yeung
  • ADAPTIVE CLAMPING CIRCUITRY
    Publication number: 20170012545
    Abstract: The present disclosure provides A DC/DC power supply system that includes a primary side and a secondary side to generate an output DC voltage from an input DC voltage. The power supply also includes adaptive clamping circuitry configured to generate an adjustable clamping voltage and/or current to limit a Vds breakdown voltage for a plurality of switches of the secondary side.
    Type: Application
    Filed: June 28, 2016
    Publication date: January 12, 2017
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Xiaopeng WANG, Kaiwei YAO
  • CONTROL OF A STARTUP CIRCUIT USING A FEEDBACK PIN OF A PWM CONTROLLER INTEGRATED CIRCUIT CHIP
    Publication number: 20170005583
    Abstract: A power supply includes a control transistor that controls a primary winding of a transformer to induce current on a secondary winding of the transformer to generate an output voltage. A pulse width modulation (PWM) controller integrated circuit (IC) chip drives the control transistor through a gate pin. The PWM controller IC chip has a feedback pin that receives a feedback signal indicative of the output voltage. A high voltage (HV) startup transistor is controlled through the feedback pin. The HV startup transistor turns ON during startup to generate a supply voltage from current received from the input voltage of the power supply. The HV startup transistor turns OFF when the supply voltage reaches a startup voltage level that is sufficient to start the switching operation of the control transistor and thereby receive operating current from an auxiliary winding of the transformer.
    Type: Application
    Filed: May 2, 2016
    Publication date: January 5, 2017
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventor: Hangseok CHOI
  • Packaged semiconductor devices and methods of manufacturing
    Patent number: 9536800
    Abstract: In one general aspect, a package can include a semiconductor die having a first terminal on a first side of the semiconductor die and a second terminal on a second side of the semiconductor die, a leadframe portion electrically coupled to the second terminal of the semiconductor die, and a molding compound. The first terminal on the first side of the semiconductor die, a first surface of the leadframe portion, and a first surface of the molding compound can define at least a portion of a first surface of the package. A second surface of the molding compound and a second surface of the leadframe portion can define at least a portion of a second surface of the package parallel to the first surface of the package, and the second surface can be on an opposite side of the package from the first surface of the package.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: January 3, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Ahmad R. Ashrafzadeh, Adrian Mikolajczak, Chung-Lin Wu, Maria Cristina Estacio
  • Reduction of degradation due to hot carrier injection
    Patent number: 9537001
    Abstract: In a general aspect, a high-voltage metal-oxide-semiconductor (HVMOS) device can include comprising a first gate dielectric layer disposed on a channel region of the HVMOS device and a second gate dielectric layer disposed on at least a portion of a drift region of the HVMOS device. The drift region can be disposed laterally adjacent to the channel region. The second gate dielectric layer can have a thickness that is greater than a thickness of the first gate dielectric layer.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: January 3, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jifa Hao, Daniel Hahn
  • DC voltage error protection circuit
    Patent number: 9538287
    Abstract: This document discusses among other things apparatus and methods for protecting circuit elements from harmful voltages. In an example, an apparatus can include an amplifier configured to receive an input signal and to provide an estimate of a first output signal, a peak detector to receive the estimate and to generate a comparison signal that is active when the amplified input signal exceeds a threshold value, and a timer configured to activate a second output signal if the comparison signal is active for at least a selected time period. The timer can include a first digital input and the selected time period can be set using a state of the first digital input.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: January 3, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Earl Schreyer
  • Ground fault circuit interrupter (GFCI) monitor
    Patent number: 9525282
    Abstract: This document discusses, among other things, a self-test (ST) ground fault circuit interrupter (GFCI) monitor configured to generate a simulated ground fault starting in a first half-cycle of a first cycle of AC power and extending into a second half-cycle of the first cycle of AC power, wherein the first half-cycle of the first cycle of AC power precedes the second half-cycle of the first cycle of AC power. Further, the ST GFCI monitor can detect a response to the simulated ground fault.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: December 20, 2016
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Bruce Armstrong
  • Audio jack system
    Patent number: 9519602
    Abstract: This application discusses a system that can include a master device and a slave device coupled to the master device via an audio jack connector. In an example, the master device and the slave device can be configured to exchange information via a single conductive path of the audio jack connector using a digital communication protocol. The single conductive path can be configured to conduct audio signals of an audio transducer and the slave device can include a depletion-mode transistor to complete a circuit including the audio transducer and the single conductive path in a first state, and to isolate the audio transducer from the single conductive path in a second state.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: December 13, 2016
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Seth M. Prentice
  • Silicon carbide bipolar junction transistor including shielding regions
    Patent number: 9515176
    Abstract: A silicon carbide (SiC) bipolar junction transistor (BJT) and a method of manufacturing such a SiC BJT is provided. The SiC BJT can include a collector region having a first conductivity type, a base region having a second conductivity type opposite the first conductivity type, and an emitter region having the first conductivity type, the collector region, the base region and the emitter region being arranged as a stack. The emitter region defining an elevated structure defined at least in part by an outer sidewall on top of the stack. The base region having a portion capped by the emitter region and defining an intrinsic base region where the intrinsic base region includes a portion extending from the emitter region to the collector region. The SiC BJT can include a first shielding region and a second shield region each having the second conductivity type.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: December 6, 2016
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Andrei Konstantinov
  • MOSFET bridge circuit
    Patent number: 9509227
    Abstract: In a general aspect, a bridge circuit can include a first bridge including a first plurality of MOSFETs and including a first input terminal and a second input terminal, and a second bridge including a second plurality of MOSFETs and including a third input terminal and a fourth input terminal. The first bridge and the second bridge can be coupled in parallel and being coupled to a first load terminal and a second load terminal.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: November 29, 2016
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Scott Pearson, Mark L. Rinehimer, Sungjin Kuen
  • MIC/GND detection and automatic switch
    Patent number: 9497559
    Abstract: This document discusses, among other things, an audio jack detection switch configured to be coupled to first and second GND/MIC terminals of an audio jack, wherein the audio jack detection switch includes a detection circuit configured to measure an impedance on the first and second GND/MIC terminals and identify each GND/MIC terminal as either a GND pole or a MIC pole using the measured impedance, and wherein the audio jack detection switch includes a switch configured to automatically couple an identified MIC pole to a MIC connection and to automatically couple an identified GND pole to a GND connection using information from the detection circuit.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: November 15, 2016
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Seth M. Prentice