Abstract: In a general aspect, an ignition circuit can include a control circuit that is coupled with an engine control unit (ECU) to receive a command signal from the ECU. The control circuit can include a multi-pulse generator configured to, in response to the command signal, generate a multi-pulse drive signal. The multi-pulse drive signal can include a first pulse cycle having a first duty cycle, a second pulse cycle having a second duty cycle, and a dwell period during which the multi-pulse drive signal continuously remains at a logic high value. The control circuit can be configured to provide the multi-pulse drive signal to an ignition switch coupled with the control circuit to receive the multi-pulse drive signal.

Abstract: A port controller includes an advertise block configured to determine a cable assembly coupled to the port controller is not compliant with a standard used by the port controller, a comparator configured to determine a current drawn from a power converter coupled to the cable assembly exceeds a capability of the power converter based on comparing a bus voltage to a threshold voltage, and a protection block configured to, in response to determining the current drawn from the power converter exceeds the capability of the power converter, cause the current drawn from the power converter to be reduced.

Abstract: A Power Factor Correction (PFC) circuit comprises an oscillator circuit. The oscillator circuit receives a valley detect signal indicating a zero current condition, determines a blanking time according to an operational cycle of the PFC circuit, and determines to initiate the operational cycle according to the valley detect signal and the blanking time. Determining the blanking time comprises selecting one of a plurality of predetermined blanking times according to a count of operational cycles of the PFC circuit. The PFC circuit may operate in a Boundary Conduction Mode or a Discontinuous Conduction Mode depending on whether a charge-discharge period is greater than the blanking time. The PFC circuit may determine, according to its output voltage, a first duration of a charging period, determine a delay time according to zero current times of previous operational cycles, and extend the first duration of the charging period by the delay time.

Abstract: This document discusses, among other things, an auxiliary self-protecting transistor circuit, system, and method configured to protect a complementary metal-oxide semiconductor (CMOS) transistor. The auxiliary self-protecting transistor circuit can include an ESD device including a gate terminal, a drain terminal, and a source terminal. The ESD device is configured to be coupled to an isolation region of a complementary metal-oxide semiconductor (CMOS) transistor, and can provide a discharge path between the isolation region of the CMOS transistor and the source terminal of the ESD device. The isolation region of the CMOS transistor can include a blocking junction, such as an n-doped isolation well (niso), a p-type well (pwell), or one or more other blocking junctions.

Abstract: A switching converter includes a synchronous rectifier and a synchronous rectifier driver that controls conduction of the synchronous rectifier. The synchronous rectifier driver turns OFF the synchronous rectifier in response to a turn-off trigger. The synchronous rectifier driver prevents the turn-off trigger from turning OFF the synchronous rectifier during a turn-off trigger blanking time that is adaptively set based on a conduction time of the synchronous rectifier.

Abstract: In a general aspect, an apparatus can include a silicon carbide (SiC) trench gate MOSFET with improved operation due, at least in part, to a reduced gate capacitance. In the SiC trench gate MOSFET, a thick gate oxide can be formed on a bottom surface of the gate trench and a built-in channel, having a vertical portion and a lateral portion, can be formed to electrically connect a vertical inversion-layer channel, such as in a channel stopper layer, to a vertical JFET channel region and a drift region.

Abstract: This disclosure provides control techniques for a resonant converter. In one embodiment, a resonant converter controller includes predictive gate drive circuitry configured to generate a predictive gate drive signal indicative of a time duration from a rising edge of a first drive signal for controlling a conduction state of a first inverter switch of a resonant converter system to a synchronous rectifier (SR) current zero crossing instant of a first SR switch of the resonant converter system, wherein the first tracking signal is based on at least the first drive signal and a voltage drop across the first SR switch. The resonant converter controller may also include SR gate drive shrink circuitry configured to generate an SR gate drive turn on delay signal to increase delay of SR on times in response to detection of a decrease in load current demand of the resonant converter system.

Abstract: In one general aspect, a system includes a material including a surface, and a magnetic sensor configured to sense a first component and a second component of a magnetic field. The first component of the magnetic field may be orthogonal to the second component of the magnetic field. The magnetic sensor may include a first sense element included on a first angled surface sloping in a first direction relative to the surface of the material, a second sense element included on a second angled surface sloping in the first direction, and a third angled surface sloping in a second direction different from the first direction where the third angled surface can be disposed between the first angled surface and the second angled surface and can exclude a sense element.

Abstract: According to one aspect of the present disclosure, there is provided a battery charging system. The battery charging system includes battery charging circuitry configured to provide charging current to a battery. The battery charging system further includes feedback circuitry configured to generate a feedback signal indicative of a battery charging condition, wherein the battery charging system is configured to control the battery charging current based on, at least in part, the feedback signal. The battery charging system further includes feed forward circuitry configured to adjust the feedback signal to decrease battery charging current when a decrease in battery current draw exceeds a threshold, and wherein the feed forward circuitry is configured to decrease the battery charging current faster than the feedback circuitry.

Abstract: An audio switch circuit includes negative feedback paths and a transistor that serves as a switching component. The negative feedback paths are turned ON to couple a source voltage and a drain voltage of the transistor to the gate of the transistor when the audio switch circuit is turned ON. The negative feedback paths reduce the slew rate of the gate-to-source voltage of the transistor, thereby slowing the turn-ON of the audio switch circuit to prevent or minimize unwanted audible noise. The negative feedback paths can be turned OFF after a period of time after the audio switch circuit is turned ON for improved total harmonic distortion.

Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Abstract: One example includes an integrated circuit including at least one electrical interconnects disposed on an elongate are extending away from a main portion of the integrated circuit and a microelectromechanical layer including an oscillating portion, the microelectromechanical layer coupled to the main portion of the integrated circuit, wherein the microelectromechanical layer includes a cap comprising a membrane that extends to the integrated circuit.

Abstract: In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.

Abstract: Implementations of semiconductor packages may include: a first substrate having a first dielectric layer coupled between a first metal layer and a second metal layer; a second substrate having a second dielectric layer coupled between a third metal layer and a fourth metal layer. A first die may be coupled with a first electrical spacer coupled in a space between and coupled with the first substrate and the second substrate and a second die may be coupled with a second electrical spacer coupled in a space between and coupled with the first substrate and the second substrate.

Abstract: An electrical circuit for a power supply includes a primary-side controller integrated circuit (IC) that outputs a drive signal on a switch pin to control a switching operation of a switch that is coupled to a primary winding of a transformer. The primary-side controller IC places the switch pin at high impedance during a sense window and turns on the switch in response to sensing a dynamic detection signal on the switch pin during the sense window. The dynamic detection signal is induced by a secondary-side controller IC by controlling switching of a switch that is coupled to a secondary winding of the transformer when the output voltage drops below a predetermined threshold during standby or other low load conditions.

Abstract: In a general aspect, a circuit can include a first resistor configured to be coupled to a first terminal of a temperature-sensitive resistance, a second resistor configured to be coupled to a second terminal of the temperature-sensitive resistance and a temperature information circuit. The temperature information circuit can be configured to: receive a first voltage from the first terminal of the temperature-sensitive resistance; receive a second voltage from the second terminal of the temperature-sensitive resistance; and provide temperature information based on the first voltage and the second voltage. The temperature information circuit can include a first comparison circuit configured to determine a difference between the first voltage and the second voltage, and a second comparison circuit configured to compare an output of the first comparison circuit to a reference.

Abstract: Apparatus and methods for interfacing with a micro-electromechanical system (MEMS) sensor are provided. In an example, an apparatus can interface circuit including an integrator circuit, a sample switch circuit, a saturation detector and a controller. The saturation detector can be configured to receive a signal indicative of an integration of charge of the sensor, to compare the signal indicative of the integration of charge to an integrator saturation threshold and to modulate a divide parameter using the comparison of the signal indicative of the integration of charge and the integrator saturation threshold. The controller can be configured to receive a clock signal and to control the sample switch circuit based on a phase of the clock signal and the divide parameter.

Abstract: Systems and methods are disclosed, including a protection multiplexer circuit configured to receive a control signal and a reference voltage, to provide the reference voltage at an output when the control signal is in a first state, and to isolate the reference voltage from the output when the control signal is in a second state. The protection multiplexer circuit includes cascaded first and second transistors, wherein the first transistor is a native transistor. Control inputs of the first and second transistors are configured to receive the control signal, a first terminal of the first transistor is configured to receive the reference voltage, and the first terminal of the second transistor is coupled to the output. Methods of operation are disclosed, and other embodiments.

Abstract: In accordance with an embodiment, a bypass charging circuit includes a pair of transistors having current carrying terminals commonly connected to form a node. An input of a comparator is coupled to the node through a switch and to a resistor. Another input terminal of the comparator is coupled for receiving a reference voltage. Optionally, a transistor may be connected to the bypass charging circuit. In accordance with another embodiment a method is provided in which bypass charging transistors are coupled to first input of a comparator in response to closing a switch. A voltage is generated at the first input of the comparator in response to closing the switch and the voltage is compared with a reference voltage. In response to the comparison, a status indicator signal is generated to indicate the presence of a low-impedance failure in one or both of the bypass charging transistors.

Abstract: In at least one general aspect, a silicon carbide (SiC) device can include a drift region and a termination region at least partially surrounding the SiC device. The termination region can have a first transition zone and a second transition zone. The first transition zone can be disposed between a first zone and a second zone, and the second zone can have a top surface lower in depth than a depth of a top surface of the first zone. The first transition zone can have a recess, and the second transition zone can be disposed between the second zone and a third zone.