Abstract: A system and method of generating flow control information for a switching node for a digital network is disclosed. The network includes a source device and a destination device interconnected by the switching node. The source device generates cells for transmission at a selected transmission rate to the destination device over a path through the switching node to transmit data in a downstream direction from the source device to the destination device. The source device further periodically generates resource management cells for transmission to the destination device over the path in the downstream direction, and the destination device returns the resource management cells over the path in upstream direction through the switching node to the source device.

Abstract: The present invention pertains to a synchronizer for transferring data from a first clock domain having a first clock signal at a first clock rate to a second clock domain having a second clock signal at a second clock rate different from the first clock domain. The synchronizer includes a mechanism for transferring data from the first clock domain to the second clock domain. Additionally, the synchronizer includes a mechanism for synchronizing the transfer of data from the first clock domain to the second clock domain by the transferring mechanism. The synchronizing mechanism is self-timing based only on the first clock rate and second clock rate without any additional control signals. The synchronizing mechanism is connected with the transferring mechanism. The present invention pertains to a system. The system includes a first clock domain having a first clock signal at a first rate. The system includes a second clock domain having a second clock signal at a second rate.

Abstract: There is shown an apparatus for switching. The apparatus for switching comprises L switching modules which switch packets, where L.gtoreq.2 and is an integer. In an embodiment, each of the L switching modules switch packets independent of any other switching module such that there is distributed switching of packets across the L switching modules. The apparatus also comprises an interconnection module which is connected to each of the L switching modules. The interconnection module that provides a passive backplane provides connectivity between the L switching modules. In an embodiment, the interconnection module provides space and time multiplexed connectivity between the L switching modules. In an other embodiment, the interconnection module is expandable without a priori knowledge of a final number of switching modules. In yet another embodiment, the interconnection module is reprogrammable in regard to connectivity between the L switching modules.

Abstract: The present invention pertains to a method for multicasting ATM cells. The method comprises the steps of reading a first ATM cell to which a first cell read pointer is pointing. Then there is the step of transmitting the first ATM cell out a first port to a first address. Next there is the step of determining whether the first ATM cell is to be transmitted out the first port to a second address. Next there is the step of reading a cell pointer pointing to a second ATM cell if the transmission of the first ATM cell out the first port to addresses is completed. The present invention pertains to a multicast system for an ATM network. The multicast system is comprised of a first ATM cell pointer mechanism associated with a first port. The multicast system also comprises at least a second ATM cell pointer mechanism associated with a second port. The multicast system is also comprised of at least a first ATM cell.

Abstract: The present invention pertains to a method for sorting. The method comprises the steps of forming a decision tree comprised of at least a first level having at least a first entry with either a first result or a second result corresponding to values as they fill a queue. Then, there is the step of reading the result in the first entry of the first level of the decision tree. Next, there is the step of choosing the value in the first entry of the first level from the queue corresponding to the result in the first entry. The present invention comprises a priority queue. The priority queue comprises an array in which elements are stored. Also, the priority queue comprises a controller which stores the elements in the array with no memory reads and a constant number of memory writes so a smallest element in the array can be identified.

Abstract: A method for scheduling when a server provides service to entities. The method includes the steps of identifying when a first entity requests service from the server. Next there is the step of providing service to an entity, such as a first entity or a second entity, as a function of virtual time. A scheduler for controlling when a server provides service to entities. The scheduler comprises a memory having times which are a function of when entities request service from the server. The scheduler is also comprised of a virtual clock that keeps track of time. The scheduler is also comprised of a controller which causes an entity to receive service from the server as a function of virtual time. Rate can also be utilized.

Abstract: A scheduler for controlling when N entities, where N is an integer greater than or equal to one, are operated upon by a server. The scheduler includes a starting time memory. The starting time memory has only arriving times which are greater than virtual time. The scheduler also includes a finishing time memory. The finishing time memory has finishing times of the N entities whose starting times are less than or equal to virtual time. Additionally, the scheduler includes a virtual clock that keeps track of virtual time so the arriving times and finishing times can be identified. Moreover, the scheduler is also comprised of a controller for choosing entities to be operated upon by the server from the finishing time memory. A method of scheduling when a server provides service to entities.

Abstract: A method for scheduling when a server provides service to entities. The method includes the steps of identifying when a first entity requests service from the server. Next there is the step of providing service to an entity, such as a first entity or a second entity, as a function of when the entity requests service from the server. A scheduler for controlling when a server provides service to entities. The scheduler includes a memory having times which are a function of when entities request service from the server. The scheduler also includes a virtual clock that keeps track of time as a function of when entities request service from the server. The scheduler also includes a controller which causes an entity to receive service from the server as a function of when the entity requests service from the server. A scheduler for scheduling when N entities each of which has a weight w, where N is an integer .ltoreq.1 and w is a real number, are served by a server.

Abstract: The present inventions pertains to a communication network. The communication network comprises an ATM network. The communication network also comprises at least two general purpose computers. Each computer has a processor, a memory in communication with the processor, and an input/output bus in communication with the processor, memory and the ATM network. The N computers communicate with each other through the ATM network and operate instructions for applications other than communications between the other computers.

Abstract: A communication network. The communication network has an ATM network portion. The communication network has an ATM cell interface in communication with the ATM network portion. The communication network also has a first general purpose computer connected to the ATM network portion and in communication with the ATM cell interface through the ATM network portion. The communication network has a second general purpose computer connected to the ATM network portion and in communication with the ATM cell interface through the ATM network portion. The first computer and second computer each execute instructions for applications other than communications between computers. The computers can communicate at 155 mb/s or 622 mb/s. The ATM cell interface can be connected to an Ethernet, or a Sonet OC-3 or an FDDI. There is a method for dispatching an ATM cell.

Abstract: The present invention pertains to an apparatus for manipulating ATM cells. The apparatus comprises a memory array in which an entire ATM cell can be read or written in one read or write cycle. The apparatus is also comprised of a mechanism for reading or writing the entire ATM cell from or into the memory array. The present invention pertains to a method for switching an ATM cell. The method comprises the steps of receiving the ATM cell at a first input port of a switch from the ATM network. Then there can be the step of storing the ATM cell in one clock cycle in a memory array of the switch. Next there is the step of reading the ATM cell in the memory array in one clock cycle. Next there is the step of transferring the ATM cell from the memory array to a first output port of the switch. Next there is the step of transmitting the ATM cell from the first output port to the ATM network. The present invention pertains to a switch for an ATM cell.

Abstract: The present invention pertains to an apparatus for manipulating ATM cells. The apparatus comprises a memory array in which an entire ATM cell can be read or written in one read or write cycle. The apparatus is also comprised of a mechanism for reading or writing the entire ATM cell from or into the memory array. The present invention pertains to a method for switching an ATM cell. The method comprises the steps of receiving the ATM cell at a first input port of a switch from the ATM network. Then there can be the step of storing the ATM cell in one clock cycle in a memory array of the switch. Next there is the step of reading the ATM cell in the memory array in one clock cycle. Next there is the step of transferring the ATM cell from the memory array to a first output port of the switch. Next there is the step of transmitting the ATM cell from the first output port to the ATM network. The present invention pertains to a switch for an ATM cell.

Abstract: A linked list for multicast in an ATM network. The linked list comprises a first cell. The linked list also comprises a plurality of read pointers. Each read pointer is associated with a port. Each read pointer points to the first cell. A multicast system for an ATM network. The system comprises a first port through which a cell passes. The system also comprises a first read pointer associated with the first port. The multicast system additionally comprises at least a second port through which the cell passes. There is at least a second read pointer associated with the second port. The multicast system is comprised of a cell to which each read pointer points. Furthermore, the multicast system is comprised of a controller for controlling when a read pointer reads a cell. The system preferably includes a plurality of cells. Each cell has a cell pointer pointing to a next cell. The plurality of cells forms a linked list.

Abstract: An ATM cell interface for dispatching an ATM cell having a header. The interface is comprised of N input ports, where N.gtoreq.1 and is an integer. The cell is also comprised of a table lookup mechanism that directs a cell from an input port to any desired destination. The table lookup mechanism has entries which identify desired destination for corresponding cells. The number of possible entries in the table lookup mechanism is less than a total number of entries supported by the ATM cell header. Preferably, a cell includes a VCI field having a value and a VPI field having a value. The table lookup mechanism preferably includes a first table which produces a first signal based on the value of the VPI field and a second level table which produces a second signal based on the value of the VCI field. The first and second signals are used to route the cell from an input port to a desired destination. Additionally, there is a method for dispatching an ATM cell.

Abstract: An ATM cell interface for dispatching an ATM cell comprising N input ports, where N.gtoreq.1 and is an integer. A table lookup mechanism directs a cell from an input port to any desired destination. The table lookup mechanism has entries which identify desired destination for corresponding cells. The number of possible entries in the table lookup mechanism is less than a total number of entries supported by the ATM cell header. The table lookup mechanism preferably includes a first table which produces a first signal based on the value of the VPI field and a second level table which produces a second signal based on the value of the VCI field. The first and second signals are used to route the cell from an input port to a desired destination. A method for dispatching an ATM cell comprising the steps of locating a table entry in a first level table corresponding to a value of a VPI field of the cell. Then there is the step of producing a first signal corresponding to the table entry.