Abstract: A light compensation scheme, an optical machine device, a display system and a method for light compensation are disclosed herein. The light compensation scheme includes a detector for inspecting a data related to a luminous flux of each of different color beams, and a controller for selectively adjusting anytime a luminosity of at least one of a plurality of pointolites and/or the transmittances of at least one part of liquid crystals disposed within a liquid crystal display panel, based on the inspected data.

Abstract: An apparatus for improving the data access reliability of flash memory is provided, including an instruction register, an address register, a flash memory control circuit, a data register, an encoder, an error correction code (ECC) generator, a signal converter, a comparator, an arbitrator, and a decoder. The instruction register and the address register are connected to a flash memory respectively for storing the access instructions and the addresses. The flash memory control circuit is connected to both instruction register and address register for controlling the access to the flash memory. The data register is connected to flash memory control circuit for loading data to be written to the flash memory. The encoder encodes the written data, and the ECC generator generates an ECC, which is written to the flash memory through the signal converter. The comparator and the arbitrator provide the comparison with ECC and informing decoder f suspicious bit values when data is read from the flash memory.

Abstract: A flash translation layer apparatus is disclosed. The flash translation layer apparatus coupled to a flash memory and a reading and writing controller, respectively. The flash translation layer apparatus includes an instruction register, a logical address register, a data register, a first auxiliary controller, a microprocessor, an address converting unit, a second auxiliary controller, a flash address register and an adjustable translation layer unit. Furthermore, the adjustable translation layer unit regards the block as a unit for a coarse-grained address translation table and regards the pages as a unit for a fine-grained address translation table, respectively. Therefore, the present invention can provide capabilities of reducing the spaces and the times of a null data collection procedure and increasing the efficiency when a logical address corresponds to a physical address.

Abstract: A parallel processing architecture of flash memory and method thereof are described. A processing unit classifies a plurality of commands to generate a first command group and a second command group respectively. The processing unit executes the first command group and the second command group. A first control unit performs the first command group to access the data stored in the first memory unit, and a second control unit simultaneously performs the second command group to access the data stored in the second memory unit for processing the data stored in the first and the second memory units in parallel.

Abstract: A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device, a second frequency calibration device and a third frequency calibration device to share the same oscillator as so to perform multi-stage clock frequency resolution calibrations for different frequency-tuning ranges. This can bring an optimal frequency resolution, greatly reduce system complexity and save element cost.

Abstract: A system and a method for configuration and management of flash memory is provided, including a flash memory, a virtual memory region, and a memory logical block region. The flash memory includes a plurality of physical erase units. Each physical erase unit is configured to include at least a consecutive segment, and each segment is configured to include at least a consecutive frame. Each frame is configured to include at least a consecutive page. Each virtual memory region is configured to include a plurality of areas, and each area is configured to include at least a virtual erase unit. The memory logical block region is configured to include a plurality of clusters, and each cluster includes at least a consecutive memory logical block.

Abstract: A scanning apparatus having dual power mode is described. The scanning apparatus includes a detection module, a switch unit, and a power controller. The detection module detects a first voltage signal and a second voltage signal for generating a detecting signal. The switch unit receives the commands from the power controller for outputting the first voltage signal and/or the second voltage signal to the image acquiring device of the scanning apparatus. The power controller determines whether the first voltage signal is detected according to the detecting signal. While the first voltage signal is detected, the power controller controls the switch unit to output the first voltage signal and/or the second voltage signal to the image acquiring device. While the first voltage signal is not exist, the power controller controls the switch unit to output the second voltage signal to the image acquiring device.

Abstract: A transmission gate circuit includes a first PMOS device, a first NMOS device, a second PMOS device, a second NMOS device, and a third transistor. A gate electrode, a first electrode and a second electrode of the first PMOS device are coupled to a first control signal, an input end, and an output end, respectively. A gate electrode, a first electrode and a second electrode of the first NMOS device are coupled to a second control signal, the input end, and the output end, respectively. A gate electrode, a first electrode and a second electrode of the second PMOS device are coupled to the first control signal, an input end, and a body electrode of the first PMOS device, respectively. A gate electrode, a first electrode, and a second electrode of the second NMOS device are coupled to the second control signal, a body electrode of the first PMOS device, and the output end, respectively.

Abstract: An electronic apparatus having switching unit is described. The electronic apparatus includes a first peripheral device, a second peripheral device and a switching unit. The first peripheral device communicates with the host unit. The second peripheral device communicates with the host unit and the first peripheral device, respectively. The switching unit switches to the host unit and the first peripheral device for allowing the host unit to access the first peripheral device via a first path. The switching unit switches to the host unit and the second peripheral device for allowing the host unit to access the second peripheral device via a second path. The switching unit switches to the first peripheral device and the second peripheral device for allowing the first peripheral device to access the second peripheral device via a third path.

Abstract: A data access apparatus and a processing system using the same are disclosed herein, which can be a power-off status to permit its storage media being accessible by another processing system. When a bus signal switching and conversion unit receives a first-level control signal, the storage media is permitted to electrically connect only with a first bus channel and to perform a conversion between a first and second bus interface formats to the accessed data and to supply a system power based on a first power signal from the processing system to the storage media. When the bus signal switching and conversion unit receives the second-level control signal, the storage media is permitted to electrically connect only with a second bus channel and to perform a conversion between a second and third bus interface formats to the accessed data, and to supply a system power based on a second power signal from the another processing system to the storage media.

Abstract: A scanning device capable of directly sending scanned images to a printing device to be printed and a related method are proposed. An image information is obtained by scanning with an image sensor module, and then stored in a storage device. When a print client detects a print request, a storing server delivers the image information to the printing device through a picture transfer protocol. Accordingly, the image information is to be printed upon a direct link between the printing device and the scanning device without needing a computer serving as a bridge.

Abstract: A display device using a surface capacitive touch panel is proposed. Upon a normal mode, an external clock generator supports a clock source; meanwhile, an external clock generator, a signal generator, a current detector, a current-to-voltage converter, an analog-to-digital converter, a filter, an interface controller, a microprocessor, and the touch-position calculators are turned on. But under a power-down mode, the external clock generator, the analog-to-digital converter, filter, the interface controller, the microprocessor, and the touch-position calculators are turned off in order to reduce power consumption. Furthermore, the external clock generator is also turned off to minimize the power consumption.

Abstract: A scanning controller, a scanning apparatus and a method for performing the scanning controller are disclosed herein. The scanning controller includes an image data processing unit, a memory control unit, a dummy line control unit, a buffer condition control unit, a motor condition control unit, a motor controlling unit and a relation control unit. Based on at least one of several predetermined contrastive relationships among each stored data amount with regard to an image buffer and its corresponding motor move timing, the relation control unit controls generation of a motor move timing from the motor controlling unit to drive a motor with variance of a scanned data generation rate and simultaneously enable determination of the dummy line control unit on which part of scanned image data should be skipped by catching of the image data processing unit.

Abstract: A memory module and a method of performing the same for access of an external electronic device are provided herein. The memory module includes a NAND-type flash memory, a dynamic random access memory (DRAM) unit, and a memory controller. The dynamic random access memory unit which is electrically connected to the NAND-type flash memory includes a dynamic random access memory and an internal power. The memory controller is used for controlling at least one of both the NAND-type flash memory and the dynamic random access memory unit. When the memory module is disconnected with the external electronic device, the internal power of the dynamic random access memory unit powers the dynamic random access memory, actively. Accordingly, data stored in the dynamic random access memory will be retained.

Abstract: A caching method provides a cashing mechanism between a logical addresses and a flash memory physical addresses. The caching mechanism involves a search tree which contains a number of internal and external translation nodes. Each external translation node points to a link list of translation units, and each translation unit records a range of logical addresses and the corresponding range of physical addresses, in addition to a version value. By traversing the search tree to reach a translation unit, the physical address of a target logical address can be determined in an efficient manner. The version value of the translation unit can be used to determine the space taken up for storing the mapping of the logical and physical addresses should be released for reuse.

Abstract: An electronic apparatus having switching unit is described. The electronic apparatus includes a first peripheral device, a second peripheral device and a switching unit. The first peripheral device communicates with the host unit. The second peripheral device communicates with the host unit and the first peripheral device, respectively. The switching unit switches to the host unit and the first peripheral device for allowing the host unit to access the first peripheral device via a first path. The switching unit switches to the host unit and the second peripheral device for allowing the host unit to access the second peripheral device via a second path. The switching unit switches to the first peripheral device and the second peripheral device for allowing the first peripheral device to access the second peripheral device via a third path.

Abstract: A slide presentation system and a method of performing the same which are capable of providing a real-time interaction among conference presenter and attendees are disclosed. When a projector projects at least one slide to as map a screened image generated from a host, an image identifying unit identifies a pointer after an image capturing unit imaging the content expressed on the projected slide. After the pointer is identified, an orienting unit detects a two-dimension coordinate value with reference to where the pointer is pointed on the projected slide as the same as the screened image of the host. Then, the two-dimension coordinate values are transmitted to the host for determining an action of the pointer according to the two-dimension coordinate value with reference to the screened image of the host. By the present invention, the pointer pointing on the projected slide can be directly implemented as functioning a mouse.

Abstract: A duplex document scanning apparatus and method thereof are described. The duplex document scanning apparatus includes a first image sensor, a second image sensor, a switch module, a data conversion unit, and a scanning control device. The first image sensor senses the first analog image signal and the second image sensor senses the second analog image signal. The switch module switches the first image sensor and the second image sensor to select the first analog image signal and the second analog image signal. The data conversion unit converts the first and second analog image signals to generate first and second digital image signals. The switch control module of scanning control device generates a switch signal to control the switch module. The scanning control device has a switch control unit and processes the first digital image signal and a second digital image signal.

Abstract: A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device and a second frequency calibration device both to share an oscillator as so to perform two-stage clock frequency resolution calibrations for generating different frequency-tuning ranges. This can bring an optimal frequency resolution and greatly reduce system complexity and save element cost.

Abstract: An external storage device accessible to a host is proposed. The external storage device includes a memory device and a processing unit. The memory device includes a protected area for storing an authentication application, a public area for storing an unlock application, and a reserved area for storing authentication information. The processing unit is used for performing an identification request from the authentication application. When the authentication information is confirmed, the host is allowed to access the protected area of the external storage device, accordingly.