Abstract: An integral heating nozzle and a syringe needle pickup vacuum tube where the nozzle moves relative to the pickup tube, FIG. 4, and where the nozzle does not move relative to the pickup tip, FIG. 1. The relative movement allows the heating gas to be directed to the solder connections while the vacuum tube may be independently moved so as to attach to the component body for removal and replacement, even when the component body is small and of different contours. In both cases the nozzle size allows components of cross section 0.01×0.01 inch to 0.05×0.05 inch to bereplaced. The opening of the nozzle accommodates removing and placing these smaller components through the nozzle. In some embodiments helium rather than air or nitrogen is used as a heating gas.

Abstract: A load balancing system for use in a distributed computing environment. An event publish and subscribe model implements the load balancing system. In the system, at least one client object publishes an event for response by a number of server hosts. A load balancing object monitors the load to the server hosts to determine a balanced distribution for the event.

Abstract: A heater box for PCB boards uses open cell metal foam as a heat sink and diffuser of heated gas. The heated gas is dispensed through a metal fabric mesh and then to the PCB to be heated. The gas is introduced under pressure and flow regulated to conduits in the metal foam diffuser. The conduits have side holes that allow the gas to diffuse evenly through the foam. The gas is heated by electrical resistance heaters built into the conduits or by a resistance heated layer between the conduits and the foam. The frame that holds the PCB to be heated and the metal fabric mesh and the heater box itself are all laterally floating with respect to each other.

Abstract: Pin-driver circuitry in each of an automatic circuit tester (10)'s digital driver/sensor circuits (36) includes a current sensor (Rsense, QS1, QS2, D1, and D2) and comparison circuit (58) that indicate whether the load current supplied by the driver exceeds a level set by a threshold input (CURRENT_VALUE). The pin-driver circuitry also includes a timer (60) whose output indicates whether the comparison circuit's output has been asserted for a length of time that exceeds a limit set by a duration input (TIME_VALUE). When it has, the tester disables the driver and thereby prevents damage that could otherwise result from excessive backdrive durations that the test-generation process did not anticipate. When no backdriving is sensed during a given burst of test signals, the tester forgoes the normal cool-down delay, thereby speeding the test process.

Abstract: In an asynchronous transaction processing method, system and computer program product, a transaction is initiated by a client object when the client object initiates a transaction context and registers with the transaction context as a participant in the transaction. The client object also publishes an event, the event including a reference to the transaction context, a reference to the client object and information. At least one server object responsive to, or subscribing to, the event registers with the transaction context identified in the event, performs a logical operation using the information provided in the event, places a vote to commit or roll back the transaction with the transaction context and calls back the client object with a response to the event using the reference to the client object included in the event.

Abstract: Pin-driver circuitry in each of an automatic circuit tester (10)'s digital driver/sensor circuits (36) includes a current sensor (R.sub.sense, QS1, QS2, D1, and D2) and comparison circuit (58) that indicate whether the load current supplied by the driver exceeds a level set by a threshold input (CURRENT.sub.-- VALUE). The pin-driver circuitry also includes a timer (60) whose output indicates whether the comparison circuit's output has been asserted for a length of time that exceeds a limit set by a duration input (TIME.sub.-- -VALUE). When it has, the tester disables the driver and thereby prevents damage that could otherwise result from excessive backdrive durations that the test-generation process did not anticipate.

Abstract: A hybrid scanner for switching internal analog buses to system pin channels. Semiconductor switches switch most scanner buses to system pin channels, but mechanical relays perform switching for at least one bus used for high-current test signals. To perform low-impedance guarding and/or high-current backdriving, the low impedance, high current bus is typically connectable to one or more overdriver circuits and a guard voltage potential through mechanical relays. The scanner is capable of supporting in-circuit tests covering the most significant regions of the fault spectrum can be made more reliable and much smaller and less costly than the scanners conventionally used in traditional broad spectrum testers. It turns out that this test-supporting capability can be achieved by adding only a few mechanical relays to an otherwise semiconductor-switch-based scanner. Only those necessary to support low-impedance and high-current test operations.

Abstract: The invention is a tester that uses a capacitive probe to test whether components that have multiple power and/or ground pins are correctly oriented relative to the signal-pin tracks on a circuit board. The tester connects, to the signal-pin track to which the pin under test is connected, a test-signal source that supplies to that pin a relatively high-voltage test signal. The tester actively guards the pin by applying to the remaining component pins, through the tester scanning system and its internal resistance, a signal that has the same voltage as that sensed by the capacitive probe. If the component is oriented such that one of the multiple power or ground pins is connected to the signal-pin track to which the test signal is applied, the test signal appears also at the other power or ground pins, since these pins are interconnected by a low impedance path through the component.

Abstract: A method for testing for short circuits between UUT pins that are nominally connected to nodes on a circuit board which the UUT is mounted and open circuits between pins and nodes nominally connected thereto. The method is used in a system that responds to the capacitances between a plate positioned above the UUT and respective nodes to which the pins are connected. A group of pins are selected such that no two pins of the group are nominally connected together. The pins are connected together in the tester and if the capacitance between the plate and the pin group is less than a first threshold an open circuit is indicated. The presence of a short circuit is indicated by a capacitance greater than a second threshold that is greater than the first threshold.

Abstract: A system for detecting open circuits in connections between pins of an integrated circuit (IC) and traces on a circuit board on which the IC is mounted makes use of a-c paths inherent in the IC. An input signal is applied to a trace to which a pin of the IC is nominally connected. An internal a-c path in the IC carries the signal to another pin. Failure to detect an output signal derived from the input signal, above predetermined thresholds, at the trace to which the latter pin is nominally connected indicates failure of a pin-to-trace connection.

Abstract: A system for generating programs for a variety of testing stations. A program generator reads a common rule set to generate test instructions for an electrical tester, an optical inspector, and an x-ray inspector. Over time, the system collects defect data that may affect the triggering of certain rules in the rule set.

Abstract: A connector, for use with an automatic test system for testing integrated circuit boards, consists of a non-conductive carrier that supports a plurality of electrically conductive contacts. In a preferred embodiment, the carrier includes a plurality of holes, each of which is filled with a wire mesh. The wire mesh compresses as necessary to accommodate variations in the lengths of the leads of the device-under-test or the wires of a system component, such as the system fixture. In an alternative embodiment, a flexible carrier supports a plurality of wires. The wires may be embedded in the carrier, or they may be wrapped partially around the carrier, to electrically connect leads proximate to top of the carrier with leads or contacts proximate to the bottom of the carrier. In a second alternative embodiment, the connector consists of a plurality of conductive drops, that are strategically placed on the ends of wires, leads or contacts.

Abstract: A probe fixture for an automatic circuit board tester has a high density array of probe pads. The array of probe pads are sized and spaced apart to ensure contact with all of the test points on the device under test (DUT). The width of the pads is made smaller than the known minimum separation of the test points, and the separation of the pads is made smaller than the known width of the test points. The pads are connected to remote contacts of the fixture. A multiplexer unit may be provided to connect the desired test circuits to different probe pads of the fixture. Using the multiplexer unit, a controller of the tester can individually test the relative connection status of each of the probes of the fixture. By comparing to the known test point layout of the DUT, the controller then determines which of the probe pads is in contact with which of the test points and proceeds with the desired test functions accordingly.

Abstract: To test for proper connections of integrated-circuit connection pins (22) on a circuit board (12) to the conductive paths to which they should be connected, a tester (10) applies signals of different frequencies to paths to be connected to different IC pins provided by the same integrated-circuit package (24). The resultant composite electric-field signal in the vicinity of the integrated-circuit package (24) is coupled to a capacitive probe (42), and the probe signal is subjected to frequency analysis (58-1, 58-2 , . . . 58-J) to determine whether the applied frequency components are present in the signal with sufficient magnitudes. If the magnitude in the sensed signal of an applied frequency component is not great enough, the tester generates an indication that the corresponding IC pin has not been properly connected.

Abstract: In a fixture (24) are mounted a plurality of probes (28) so disposed as to enable them simultaneously to contact test points on a circuit board (26) to be subjected to an in-circuit test. Wiring (30) connects the probes (28) to respective fixture pins (22) that mate with the system pins (20) by which a general-purpose tester (12) provides connections to various test instruments (14). The wiring (20) is so provided that certain of the probes (28) are wired together and thus require fewer system pins (20) than there are probes (28).

Abstract: In one aspect, the present invention provides a system for determining the operation of an integrated circuit, comprising:receiving means (4,5) for receiving and storing information about said integrated circuit and for pre-storing a range of stimuli to be applied to a model of said integrated circuit;selecting means (6) for selecting at least one stimulus from said range;a first translator (8) for translating said selected stimulus from a reference language into an alien language;an alien simulator (12) for applying said translated stimulus to an alien model of said integrated circuit and obtaining a response to said translated stimulus;a second translator (14) for translating the said response from said alien language to said reference language; andstore means (16) for storing said translated response, said stimulus and response portraying operation of the integrated circuit.

Abstract: In a capacitive-probe assembly used in an automatic circuit tester (10) to sense varying electric fields that result adjacent to integrated-circuit packages (32) during tests of circuit boards (16), a spacer comprising resilient cellular material has a double-sided printed-board attached to it that provides the probe plate (52) to which the device signals are capacitively coupled. The spacer (44) is in turn mounted on a chip-probe mounting surface (30) provided by the tester's fixture (14). The result is a robust fixture assembly that is easy to manufacture.

Abstract: When an automatic circuit tester (10) detects that a fault has occurred in a circuit board (14), it applies to the circuit board (14) a sequence of vectors that differs from the test sequence (T.sub.n, T.sub.n+1) by which the fault detection occurs only in that each vector's component that corresponds to an input pin in question on the board device under test maintains a level that simulates an open circuit at that input pin. If the resultant response differs from the response to the original test sequence, the input pin can often be ruled out as one at which a fault has occurred. In this way, many open-circuit faults at input pins can be diagnosed without special probing, even when several such faults occur simultaneously.

Abstract: In a method for testing whether a pin (12) of an electronic component (14) on a circuit board under test (18) has been properly connected to a circuit-board track (16), a source (20) drives the track (16), and a capacitive probe (34) located above the component (14) generates a resultant output. The pin (12) is determined to be connected correctly if that output exceeds a threshold determined for that pin (12) during a training process in which similar measurements have been made on a known good board for that pin and other pins on the same electronic device. The threshold is determined by dividing the capacitance measurement made during the training process for that pin into connection-dependent and connection-independent parts, the latter being the part that would result even in the absence of a proper pin connection.

Abstract: A bit-error-rate detector (20) in a test set (10) for a frame-based communications channel employs a pseudo-random-number generator (46) at the channel's output end that generates a sequence the same as that produced by a pseudo-random-number generator (16) at the input end, but typically with a timing offset. A chain of delay circuits (38, 40, 42, and 44) receives the channel output. Each delay circuit imposes a delay equal to a single frame time and produces a respective output. One such output (CENTER) is normally compared in an XOR gate (52) with the output of the output-end pseudo-random-number generator (46). The XOR gate (52) applies signals indicative of any symbol mismatches to a shift register (88), which forwards them, after a delay, to a bit-error-rate counter (90).