Abstract: A test method for a switch matrix (10) of a liquid-crystal display employs a signal source (40, 42) to drive a row line (20) of the matrix and employs current sensors (56, 58, and 60) to measure the resultant current flow. Errors are detected by observing departures of the measured currents from expected values. To increase the sensitivity of the current measurement to the capacitance in the location at which the associated column line (14, 16, or 18) intersects the driven row line (20), return connections for the source (40, 42) are made directly to the contact pads (26, 28) of the row lines not currently being driven and column lines not currently being sensed.

Abstract: A method of performing in-circuit testing of interior points of circuit boards containing both boundary-scan and non-scan components that utilizes the boundary-scan facility. The testing procedure involves isolation of the non-scan components and either driving or sensing voltages at physically accessible test sites. The method permits use of isolation and multiplexing solutions that are ordinarily developed for in-circuit testing of board components, resulting in efficient design and implementation of interconnect tests.

Abstract: An automated circuit board testing system, for performing in-circuit, functional or cluster tests, takes backdrive stress into account in selecting appropriate isolation methods for digital devices during the design of the test protocol. In other words, the design of the test includes an analysis of the circuit board and its components, and of the available methods to isolate the device- or function-under-test from the rest of the circuit board. The analysis includes a calculation of stress currents on upstream components resulting from backdriving, and a selection of methods from those available which will produce stress currents below a pre-selected level. In another aspect of the invention, the safe maximum run-time for the test using the available methods is computed.

Abstract: An automatic circuit tester (10) includes a scanner bus (50) that includes series of signal-path links (70A-H, 72A-H) and connectors (51) into which scanner boards (46, 47) are plugged. Each scanner board includes switches (74A-H, 76A-H, and 78A-H) that in different states can (i) connect together the links on opposite sides of the scanner board so as to forward signals along the link sequence and (ii) connect the link on one side to an instrument (18) or system pin (24) while isolating the link on the other side from the first link and the instrument or system pin.

Abstract: An automatic circuit tester (10) employs a scanner (20) embodied in a group of interconnected main scanner boards (46, 47) that provide switching by means of mechanical relays. In order to provide a cross-point matrix and structure without unacceptable stub lengths, the relays are mounted on auxiliary boards (114) that extend transversely from the surface of each main board (46, 47). The main scanner boards plug into a scanner bus (50) in such a manner as to permit them to connect or disconnect adjacent links (70A-H, 72A-H) in sequences of links in the scanner bus (50).

Abstract: An output circuit (62) for generating a signal in the form of a voltage between an output signal node and an output reference node (60) receives power from a pair of voltage regulators (Q1 and 68, Q2 and 70). The regulators are connected in power-circuit series so as to be powered by the difference between the output potentials of two opposite-polarity supplies without a direct low-impedance connection between the power-supply ground (73) and the output reference node (60). To avoid large current flow in any external path between an output reference node (60) of an electronic circuit and the ground node (73) of its power supply, a current sensor (R1, R2, 86) senses the net current that the power supplies provide to the circuitry that includes the regulators, and it controls variable loads (Q3, Q4) that selectively drive current into and draw current from the reference node (60) so as to drive the net current to zero.

Abstract: An automatic circuit tester (10) employs a scanner (20) embodied in a group of interconnected scanner boards (46, 47) that provide switching by means of mechanical relays. The scanner boards plug simultaneously into respective instrument boards (44) and into a common scanner bus (50) separate from an instrument bus (38) that carries the signals that control the instruments on the instrument boards (44). The scanner bus provides a common pathway for signals to travel between instruments or system pins to which one scanner board is connected and those to which another is connected. It also provides scanner-control paths so that the instrument boards to which the scanner boards are connected to not need to provide such paths and thus do not need to be custom-designed for the particular tester in which they are used.

Abstract: An AC signal source (26) in series with a variable DC source (34) drives a gate line of an LCD-display drive matrix (10), and current meters (28, 30, 32) monitor the resultant currents in the drain lines. By comparing the thus-measured transadmittance both with and without enabling values of the DC-source output, one can test the matrix (10) for defects.

Abstract: A time-interval meter (10) employs a counter (16) to count the number of cycles of the output of an oscillator (18) that occur between a pulse on a start input line (12) and a subsequent pulse on a stop input line (14). The result is a coarse measurement. A filter (28) filters the output of the oscillator (18) to produce a sinusoidal signal, and the meter (10) refines the coarse measurement by employing analog-to-digital converters (20 and 22) to measure the values assumed by the sinusoidal signal at the occurrences of the start and stop pulses. A calculation circuit (24) employs an inverse trigonometric function of the converter outputs to determine the difference between the phases of the sinusoidal signal at the occurrences of the start and stop pulses, and it adds the time difference associated with this phase difference to the coarse measurement indicated by the cycle count to yield a total interval duration.

Abstract: A test fixture useful in testing printed circuit boards requires wire-wrapping only on a single side of a single board and is characterized by a reduced signal path length. The test fixture is provided with a translator device for conducting signals between system contact points in a testing system and contact points corresponding to selected locations on a unit-under-test ("UUT"). The translator device includes extended system pins, non-extended system pins, UUT pins and through-posts. On one side of the translator board, the UUT pins are wire-wrapped to the extended system pins wherever space allows, and otherwise to the through pins. The through pins make electrical contact to the non-extended system pins by means of conductive pads disposed on the other side of the translator board. A method of fabricating such a test fixture includes the step of computing optimal UUT and through-post locations.

Abstract: A technique for automatically diagnosing the failure of electronic devices connected to share a common bus. All bus devices are first disabled, and the bus is examined to determine if a failed device is interfering with normal operation by causing the bus to be stuck at a logic high or a logic low level. If the bus is stuck low or high, a forcing voltage nearly equal to either V.sub.ol or V.sub.oh, respectively, is applied to the bus, with all devices still disabled. A disabled bus current is then measured. One at a time, the bus devices are enabled, and the current on the bus measured to determine an enabled bus current. If, for a particular device, the enabled bus current exceeds the disabled bus current by a predetermined amount depending on the drive current specification of the device, it is concluded that the particular device is operating properly.

Abstract: A method for calibrating measurement or analysis systems that is externally traceable, simple, and repeatable, which is particularly amenable to computer control, and a unique programmable phase-gain amplifier which is especially suited for use in the calibration method, are disclosed. Alternatively, a programmable sample clock delay technique is disclosed to provide phase calibration. The method employs an externally traceable digital voltmeter to measure the magnitude of the signal being applied to an input channel of the measurement system; and obtains a digital representation of the output of the channel. When the input magnitude does not match the output magnitude, the programmable phase-gain amplifier gain is adjusted. These adjustments are made for each range of each channel.

Abstract: To avoid component damage due to the presence of an incorrect voltage on the power bus of an electrical system when the system's power supply is turned on, the system carries out a self-testing procedure before power up to detect fault-indicating low impedance paths in the power bus. For this, the system includes a test power supply which delivers to the bus during the self-testing routine test voltages which are much lower than those supplied to the bus by the main supply. In accordance with the self-testing routine, the main power supply is turned on upon completion of the routine only if no low impedance paths are detected in the bus. As the supply voltages are applied to the bus, they are compared with preselected limits. If any voltage is not within its limits, the system provides an indication to that effect and/or shuts down the system.

Abstract: In order to determine whether the proper type of integrated circuit is located in the proper position (16) and the proper orientation, a power source (18) applies a potential difference to circuit paths (26 and 28) that will properly power an integrated circuit (14) if it is of the proper type and in the proper orientation. Without attempting to place the integrated circuit (14) in a predetermined state, a test system (10) employs a milliammeter (32) first to measure the current driven by an output terminal (30) and then to measure the current that the output terminal (30) draws from a bias source (40). If a current level consistent with an active output terminal is measured in either step, a control circuit (38) concludes that the integrated circuit (14) is of the proper type and properly positioned. Otherwise, the control circuit (38) concludes that an integrated circuit is missing, of the wrong type, or improperly oriented.

Abstract: A circuit tester (12) tests an electronic circuit (10) to determine which of a number of bus devices (16, 18, and 20) on the circuit (10) is stuck in an asserting state and is thus keeping a bus (14) at the asserted voltage level. A back-driving source (21) back-drives the bus (14) to its de-asserted level, and each of the devices (16, 18, and 20) is enabled individually in succession. When a device is enabled, a current meter (22) determines whether the bus current increases as a result. If so, the given device is not the defective device that is keeping the bus asserted. If there is no current change, the device is the defective one. A current limit is imposed on the back-driving source (16). This limit depends on the particular device being enabled; the limit is set higher than the quiescent assertion current on the bus but less than the sum of the quiescent current and the assertion-current capacity of the device being enabled.

Abstract: A probe is disclosed which may be used to test the optical functions of a wide variety of light-emitting devices or displays. The probe comprises a fiber optic cable and a detector. When the probe is placed in close proximity to a light source, the detector produces an electrical output signal whose magnitude is indicative of the intensity of the light conducted by the fiber optic cable. The output signal is electrically compatible with conventional automatic test equipment inputs. As a result, a plurality of probes may be arranged in a test fixture which may be connected directly to an automatic test unit, thereby permitting the automatic testing of the optical functions of a device under test.

Abstract: A guide probe test system for isolating faults in PC boards performs a "variable time domain" analysis by comparing probed data with stored reference data of waveforms of a known good UUT (unit under test) that are augmented by (1) insertion of shift coefficients to compensate for non-synchronization of the probed data with a start event, and (2) insertion of jitter coefficients to compensate for timing variations in the probed data due to allowable component propagation delay tolerances and/or an asynchronous clock. The insertion of the shift and jitter coefficients creates failure ranges within which mismatches of the probed data with the reference data are treated as possible rather than absolute failures. The UUT is partitioned into measurement sets containing nodes with common stimulus and synchronization to allow the analysis to break feedback loops and isolate faulty components.

Abstract: A method and apparatus for converting a digital signal into a band-limited analog signal with variable bandwidths, a high level of performance, high spurious frequency rejection, and simple implementation, employing polyphase interpolating digital filters, a fixed-sampling rate digital to analog converter, and a fixed-frequency analog low-pass filter.

Abstract: A time-measurment circuit (10) employs time-expansion circuits (13 and 14) to expand the initial and final portions of the duration of an event so as to measure more precisely those segments of time that typically are not integral numbers of clock periods in length. Each time-expansion circuit (13 and 14) employs a single capacitor (34), which it charges at a rapid rate during the initial or final time segment to be measured and then discharges at a much lower rate. The clock periods that occur during the time required for charging and discharging are counted, so the initial and final segments are measured with greatly enhanced resolution. An emitter-coupled-logic integrated circuit (54) performs the charging of the capacitor (34) by drawing current through its V.sub.CC1 l terminal ( 62).

Abstract: This apparatus controls the execution and content of computer programs in equipment containing a computer by causing the transfer of program data elements, including computer instructions, with a memory means of the apparatus, wherein the selection of data for transfer is effected either by the computer, operating in a normal manner, or by the apparatus, which may shift data selection between these two selection options so that the computer ceases selection of data constituting one program and begins selecting data of another program. While data elements are being transferred with the computer, other elements of the memory means are available for examination and modification such that new programs, the content of which may depend on the results of prior program execution, can be loaded, executed, and examined without interrupting, delaying, halting, or otherwise disturbing the instruction flow of the computer equipment.