Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices incorporating reference cells for achieving high sensing yield. The present disclosure provides a memory device including a main cell structure including a switching element arranged between a pair of conductors, and a reference cell structure electrically coupled to the main cell structure. The reference cell structure includes a switching element arranged between a pair of conductors, in which the switching element of the reference cell structure has a dimension that is different from a dimension of the switching element of the main cell structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture. The structure comprising a vertical silicon controlled rectifier (SCR) connecting to an anode, and comprising a buried layer of a first dopant type in electrical contact with an underlying continuous layer of a second dopant type within a substrate.

Abstract: The present disclosure generally relates to semiconductor devices for use in optoelectronic/photonic applications and integrated circuit (IC) chips. More particularly, the present disclosure relates to photodiodes such as avalanche photodiodes (APDs) and single photon avalanche diodes (SPADs).

Abstract: A device may include a substrate, and an interlevel dielectric arranged over the substrate. The interlevel dielectric may include a first interlevel dielectric layer in an interconnect level i, the first interlevel dielectric layer having a first interconnect and a second interconnect therein. A nitride block insulator may be arranged over the first interlevel dielectric layer and over the first interconnect and the second interconnect. An opening may be arranged in the nitride block insulator, the opening extending through the nitride block insulator to expose a surface of the first interconnect in the first interlevel dielectric layer. A contact plug may be arranged in the opening of the nitride block insulator. The contact plug at least lines the opening and prevents out-diffusion of conductive material from the first interconnect. A thin film of a passive component may be arranged over the nitride block insulator and over the contact plug.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture. The structure includes a vertical silicon-controlled rectifier (SCR) connecting to an anode, and includes a buried layer of a first dopant type in electrical contact with an underlying buried layer a second dopant type split with an isolation region of the first dopant type within a substrate.

Abstract: Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a structure for a laterally-diffused metal-oxide-semiconductor device. The structure includes a drift well in a semiconductor substrate, source and drain regions in the semiconductor substrate, a gate dielectric layer on the semiconductor substrate, and a buffer dielectric layer on the semiconductor substrate over the drift well. The buffer dielectric layer includes a first side edge adjacent to the drain region, a second side edge adjacent to the gate dielectric layer, a first section extending from the second side edge to the first side edge, and a plurality of second sections extending from the second side edge toward the first side edge. The first section has a first thickness, and the second sections have a second thickness less than the first thickness. A gate electrode includes respective portions that overlap with the buffer dielectric layer and with the gate dielectric layer.

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a substrate having an active region, a source region, a drain region, and a floating gate. The source region and the drain region may be arranged in the active region, the drain region may be arranged adjacent to the source region. The source region and the drain region may define a channel region therebetween. The floating gate may be arranged over the active region, and may include a first section over the channel region, a plurality of second sections over the drain region, and a connecting section arranged between the first section and the plurality of second sections.

Abstract: A transistor may include a buffer layer, source and drain contacts on the buffer layer, a barrier layer on the buffer layer, a conductive member on the barrier layer, a dielectric stack, and a gate metal. The barrier layer may be between the source and drain contacts. The conductive member may include a p-doped III-V compound. The dielectric stack may be on the barrier layer and on the conductive member. The dielectric stack may include a first dielectric layer and a second dielectric layer on the first dielectric layer. First and second trenches may extend through the dielectric stack to the conductive member and to the first dielectric layer, respectively. The gate metal may be on the dielectric stack, and may contact the conductive member through the first trench and may contact the first dielectric layer through the second trench.

Abstract: Structures including a magnetic-tunnel-junction layer stack and methods of forming such structures. The structure comprises a magnetic-tunneling-junction layer stack including a reference layer, an antiferromagnetic layer, a free layer positioned between the reference layer and the antiferromagnetic layer, and a tunnel barrier layer positioned between the reference layer and the free layer. The antiferromagnetic layer has a static magnetic field with a magnetization, and the antiferromagnetic layer is antiferromagnetically coupled to the free layer.

Abstract: Structures for a high-electron-mobility transistor and methods of forming a structure for a high-electron-mobility transistor. The high-electron-mobility transistor has a first semiconductor layer, a second semiconductor layer adjoining the first semiconductor layer along an interface, a gate electrode, and a source/drain region. An insulator region is provided in the first semiconductor layer and the second semiconductor layer. The insulator region extends through the interface at a location laterally between the gate electrode and the source/drain region.

Abstract: An electrostatic discharge (ESD) protection device including: a substrate including: a first, second and third doped regions, the second doped region disposed between the first and third doped regions, the second doped region has a first conductivity type and a first doping concentration and the first and third doped regions have a second conductivity type and a second doping concentration; first and second doped terminal regions disposed within the first and second doped regions, respectively; and a doped island region disposed within the second doped region, the first and second doped terminal regions and doped island region have the second conductivity type and a third doping concentration, the third doping concentration higher than the first and second doping concentrations; and conductive terminals respectively coupled to the doped terminal regions; and an insulation layer arranged on the substrate between the conductive terminals and covering at least the second doped region.

Abstract: A semiconductor device may include a substrate having a source region and a drain region, and a gate arranged over the substrate and between the source region and the drain region. A first interlevel dielectric (ILD) layer may be at least partially arranged over the substrate and the gate. A conductive field plate may be arranged over the first ILD layer. At least one drain contact may extend through the first ILD layer over the drain region and may be coupled to the conductive field plate. A drain captive structure may be disposed in the first ILD layer and adjacent to the drain region, the drain captive structure having a trench comprising an air gap, wherein the drain captive structure is laterally spaced apart from sidewalls of the gate.

Abstract: A device includes a buried oxide layer disposed on a substrate, a first region disposed on the buried oxide layer and a first ring region disposed in the first region. The first ring region includes a portion of a guardring. The device further includes a first terminal region disposed in the first ring region, a second ring region disposed in the first region and a second terminal region disposed in the second ring region. The first terminal region is connected to an anode and the second terminal region is connected to a cathode. The first region has a graded doping concentration. The first region, the second ring region and the second terminal region have a first conductivity type, and the first ring region and the first terminal region have a second conductivity type. The first conductivity type is different from the second conductivity type.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises mono-crystal silicon based material; an intrinsic base under the emitter region and comprising semiconductor material; and an extrinsic base surrounding the emitter and over the intrinsic base.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises silicon based material; an intrinsic base; and an extrinsic base overlapping the emitter region and the intrinsic base; an extrinsic base overlapping the emitter region and the intrinsic base; and an inverted “T” shaped spacer which separates the emitter region from the extrinsic base and the collector region from the emitter region.

Abstract: A memory device may be provided. The memory device may include a first electrode including a first side surface and a second side surface opposite to the first side surface; a passivation layer arranged laterally alongside the first side surface of the first electrode; a switching layer arranged laterally alongside the passivation layer; and a second electrode arranged along the switching layer.

Abstract: The disclosed subject matter relates generally to methods of forming a semiconductor device, such as a moisture sensor. A plurality of electrodes and a bond pad are formed in a dielectric region. A passivation layer is formed on each electrode in the plurality of electrodes and the bond pad. A barrier layer is formed on the passivation layer. A plurality of trenches are formed to extend through the barrier layer and into the dielectric region. Formation of the trenches simultaneously exposes an upper surface of the bond pad. A moisture sensitive dielectric layer is formed on the barrier layer. Formation of the moisture sensitive dielectric layer also fills the trenches to form a plurality of projections, each projection being formed between two electrodes in the plurality of electrodes.

Abstract: Structures for a silicon-controlled rectifier and methods of forming a structure for a silicon-controlled rectifier. The structure includes a first well and a second well in a semiconductor substrate. The first well has a first conductivity type, and the second well has a second conductivity type opposite to the first conductivity type. The structure further includes a first terminal having a doped region that has a portion in the first well, and a second terminal including a second doped region that has a portion in the first well and a third doped region in the second well. The first and second doped regions have the second conductivity type, the third doped region has the first conductivity type, and the second doped region is positioned in a lateral direction between the first doped region and the third doped region.

Abstract: The disclosed subject matter relates generally to structures, memory devices and a method of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices with an electrode having tapered sides. The present disclosure provides a memory device including a first electrode having a tapered shape and including a tapered side, a top surface, and a bottom surface, in which the bottom surface has a larger surface area than the top surface, a resistive layer on and conforming to at least the tapered side of the first electrode, and a second electrode laterally adjacent to the tapered side of the first electrode, the second electrode including a top surface and a side surface abutting the resistive layer, in which the side surface forms an acute angle with the top surface.

Abstract: A resistive random access memory (RRAM) device may be provided, including: a base layer, a vertical electrode stack arranged over the base layer, where the vertical electrode stack may include alternating mask elements and first electrodes, and each first electrode may include an extended portion extending beyond at least one side surface of at least one mask element adjoining the first electrode, a switching layer arranged along the extended portion of each first electrode and along the at least one side surface of the at least one mask element adjoining the first electrode, and a second electrode including a surface in contact with the switching layer. The RRAM device may have a 3D structure.