Patents Assigned to HAESUNG DS CO., LTD
  • Publication number: 20190122968
    Abstract: Provided are a semiconductor package substrate and a manufacturing method thereof having improved pattern accuracy and product reliability with simple manufacturing processes. The semiconductor package substrate includes a base substrate having a conductive material, and including a first area, on which chips are mounted, including first recesses or first trenches in a surface, and a second area contacting the first area and including dummy recesses or dummy trenches in a surface; and a resin filled in the first recesses or the first trenches and the dummy recesses or the dummy trenches.
    Type: Application
    Filed: November 14, 2016
    Publication date: April 25, 2019
    Applicant: Haesung DS Co., Ltd.
    Inventors: In Seob BAE, Sung Il KANG
  • Publication number: 20190057930
    Abstract: A semiconductor package substrate, in which a base substrate having an upper surface and a lower surface and formed of a conductive material is filled with resin formed of an insulating material, includes a die pad formed of the conductive material on the upper surface and a lead arranged on the upper surface by being electrically separated from the die pad and comprising a bonding pad that is a wire bonding area. A protrusion protruding toward the lower surface is formed in a central area of the bonding pad. A central thickness of the bonding pad is greater than a peripheral thickness of the bonding pad.
    Type: Application
    Filed: November 10, 2016
    Publication date: February 21, 2019
    Applicant: HAESUNG DS CO., LTD.
    Inventors: In Seob BAE, Sung Il KANG
  • Patent number: 10196367
    Abstract: Provided are a bleed-out preventing agent and a composition for preventing bleed-out including the same.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: February 5, 2019
    Assignee: HAESUNG DS CO., LTD
    Inventors: Soeng Ick Kim, Dong-Soo Shin
  • Publication number: 20180190406
    Abstract: Provided is an electric wire structure including a copper (Cu) electric wire extending in a direction; and a graphene coating layer formed on an outer portion of the Cu electric wire to surround the Cu electric wire, wherein the Cu electric wire includes Cu having a purity of 99.9% or greater.
    Type: Application
    Filed: August 2, 2016
    Publication date: July 5, 2018
    Applicant: Haesung DS CO., Ltd.
    Inventors: Dong Kwan WON, Hyun Tae LIM, Jae Chul RYU
  • Publication number: 20180172520
    Abstract: Provided is a temperature sensor patch including: a base material having a lower surface that is an adhesive surface; a temperature sensor layer arranged on the base material, and including a temperature sensor at a side thereof and a connection terminal connected to the temperature sensor at the other side thereof; a cover layer configured to cover the temperature sensor layer and including a first opening exposing the connection terminal; and a module holder disposed inside the first opening, wherein a portion of the temperature sensor layer, where the connection terminal is arranged, is disposed on the module holder.
    Type: Application
    Filed: July 17, 2017
    Publication date: June 21, 2018
    Applicant: Haesung DS CO., Ltd.
    Inventors: Jae Hoon JANG, Ho Sang YU, Jin Woo LEE
  • Patent number: 9671352
    Abstract: Provided are a reel-to-reel inspection apparatus and method. The reel-to-reel inspection apparatus includes: an unwinding unit configured to unwind a roll-shaped object; a first inspection unit configured to photograph a surface of the object discharged from the unwinding unit; a second inspection unit configured to photograph another surface of the object which has passed through the first inspection unit; a marking unit configured to indicate a mark on the object which has passed through the second inspection unit; and a winding unit configured to wind in a roll shape the object which has passed through the marking unit.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: June 6, 2017
    Assignee: HAESUNG DS CO., LTD
    Inventors: Suck-Ha Woo, Je-Youn Jee, Ki-Sang Moon
  • Patent number: 9532466
    Abstract: A method of manufacturing a multi-layer circuit board includes: forming a first circuit layer on a first surface of a first prepreg; stacking a second prepreg on a first surface of the first circuit layer; and forming at least one of a second or a third circuit layer on at least one of a first surface of the second prepreg and a second surface opposite of the first surface of the first prepreg, wherein, in the stacking of the first prepreg, the first prepreg and the second prepreg are semi-cured.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: December 27, 2016
    Assignee: HAESUNG DS CO., LTD.
    Inventors: Sang-min Lee, Soon-Chul Kwon
  • Patent number: 9460986
    Abstract: A method of manufacturing a semiconductor package substrate has a simplified process and an upper and lower pattern alignment problem is solved. A semiconductor package substrate is manufactured by the method. The method of manufacturing a semiconductor package substrate includes forming a first groove in one surface of a base substrate of a conductive material, filling the first groove with resin, and etching another surface of the base substrate to expose the resin filling the first groove.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: October 4, 2016
    Assignee: HAESUNG DS CO., LTD
    Inventors: Sung Il Kang, In Seob Bae, Min Seok Jin
  • Patent number: 9299588
    Abstract: There is provided a method of manufacturing a lead frame, the method including: preparing a lead frame raw material; forming openings in the lead frame raw material so that the lead frame material includes: a die pad; a die pad supporting portion supporting the die pad; a rail portion supporting the die pad supporting portion; a lead supporting portion having both ends fixed to the die pad supporting portion; and a plurality of leads having a first end connected to the rail portion and a second end connected to the lead supporting portion; plating the lead frame raw material having the openings with a plating layer; and removing the lead supporting portion.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: March 29, 2016
    Assignee: HAESUNG DS CO., LTD
    Inventor: Jeung-Il Kim
  • Patent number: 9257310
    Abstract: Provided is a method of manufacturing a circuit board. The method includes: preparing a base substrate including a core layer and a first conductive layer that is formed on at least one surface of the core layer and includes an internal circuit pattern; forming a build-up material to cover the first conductive layer; forming in the build-up material at least one cavity through which the core layer and the first conductive layer are exposed; forming a laminated body by curing the build-up material in which the at least one cavity is formed; and forming a second conductive layer including an external circuit pattern on an outer surface of the laminated body.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: February 9, 2016
    Assignee: HAESUNG DS CO., LTD.
    Inventor: Sang-Min Lee
  • Patent number: 9171789
    Abstract: There is provided a lead frame including a plurality of plating layers formed on both an upper surface and a lower surface of a base material including a metal, wherein an upper outermost plating layer of an upper part of the lead frame is a silver plating layer including silver, and a lower outermost plating layer of a lower part of the lead frame is a gold plating layer including gold.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: October 27, 2015
    Assignee: HAESUNG DS CO., LTD
    Inventors: Dong-Il Shin, In-Seob Bae, Se-Chuel Park
  • Patent number: 9173300
    Abstract: A method of manufacturing a printed circuit board (PCB) and the PCB are provided. The method includes: filling a resin in a via-hole formed at a substrate from one surface side of the substrate; emitting light for a predetermined period of time to the resin filled in the via-hole from the other surface side of the substrate; and applying another resin on the other surface of the substrate.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: October 27, 2015
    Assignee: HAESUNG DS CO., LTD
    Inventors: Jeong-Hoon Seol, Youn-Kwon Jung, Sang-Kun Kim
  • Publication number: 20150266835
    Abstract: Provided are a bleed-out preventing agent and a composition for preventing bleed-out including the same.
    Type: Application
    Filed: March 12, 2015
    Publication date: September 24, 2015
    Applicant: HAESUNG DS CO., LTD
    Inventors: Soeng Ick KIM, Dong-Soo SHIN
  • Patent number: 9142495
    Abstract: The present invention provides a lead frame having excellent solder wettability and solderability, that is well-bonded to a copper wire, and manufactured with low cost, and a semiconductor package manufactured by using the same. The lead frame includes: a base material; a first metal layer formed on at least one surface of the base material, the first metal layer comprising nickel; a second metal layer formed on a surface of the first metal layer, the second metal layer comprising palladium; and a third metal layer formed on a surface of the second metal layer, the third metal layer comprising silver.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: September 22, 2015
    Assignee: HAESUNG DS CO., LTD.
    Inventors: Sung-Kwan Paek, Dong-Il Shin, Se-Chuel Park
  • Publication number: 20150194323
    Abstract: A method of manufacturing a semiconductor package substrate has a simplified process and an upper and lower pattern alignment problem is solved. A semiconductor package substrate is manufactured by the method. The method of manufacturing a semiconductor package substrate includes forming a first groove in one surface of a base substrate of a conductive material, filling the first groove with resin, and etching another surface of the base substrate to expose the resin filling the first groove.
    Type: Application
    Filed: January 5, 2015
    Publication date: July 9, 2015
    Applicant: HAESUNG DS CO., LTD
    Inventors: Sung Il KANG, In Seob BAE, Min Seok JIN
  • Patent number: D833305
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: November 13, 2018
    Assignee: Haesung DS CO., LTD.
    Inventors: Jae Hoon Jang, Ho Sang Yu, Jin Woo Lee
  • Patent number: D833306
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: November 13, 2018
    Assignee: Haesung DS CO., LTD.
    Inventors: Jae Hoon Jang, Ho Sang Yu, Jin Woo Lee
  • Patent number: D842136
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: March 5, 2019
    Assignee: Haesung DS CO., LTD.
    Inventors: Jae Hoon Jang, Ho Sang Yu, Jin Woo Lee