Abstract: A logic signal transmitting circuit includes a CMOS inverter, a first transistor switch and an inverter. The CMOS inverter includes a p-type transistor and an n-type transistor and is configured for inverting an input signal. The first transistor switch is connected to an input of the CMOS inverter and controlled by the input signal. The inverter is connected between the p-type transistor and the first transistor switch, in which the inverter turns off the p-type transistor when the first transistor switch is turned on and the inverter turns on the p-type transistor when the first transistor switch is turned off.

Abstract: A voltage trimming circuit is provided. The voltage trimming circuit has an input stage, an up-trimming resistor ladder, a down-trimming resistor ladder and a control means. The input stage has a first input, a second input and an output, wherein the first output is to receive an input voltage, the second input is connected to a connection point and the output is to provide an output voltage based on a difference between the voltage of the first and the second input. The up-trimming resistor ladder is connected between the output of the input stage and the connection point and the down-trimming resistor ladder connected between a ground potential and the connection point. The control means controls the resistance of the up-trimming and the down-trimming resistor ladder to up-trim or down-trim the output voltage.

Abstract: A delay circuit includes current sources, switches, a transistor switch, a charging unit and a comparator. Each of the switches is provided for receiving an enable signal to activate and convey one of the current sources. The transistor switch is activated for pulling down voltage of an operating node coupled to the switches. The charging unit provides an operating voltage for the operating node based on one of the current sources when the transistor switch is deactivated and one of the switches is activated to convey one of the current sources to the charging unit. The comparator is provided for comparing the operating voltage with a reference voltage.

Abstract: An over-current protection circuit includes a voltage generating unit and a comparing unit. The voltage generating unit is configured for receiving a first voltage and generating a reference voltage. The reference voltage has an offset positively dependent on temperature and negatively dependent on the first voltage, and the offset of the reference voltage varies along with another offset varying within a sense voltage sensed by the over-current protection circuit. The comparing unit is configured for comparing the reference voltage with the sense voltage to output a control signal for de-asserting the sense voltage when the sense voltage is correlated to an over-current condition of the sense voltage exceeding the reference voltage. A driver is also disclosed herein.

Abstract: A current regulating circuit includes a transistor and an operational amplifier. The transistor receives a load current and generates a feedback voltage corresponding to the load current. The operational amplifier receives a reference voltage and the feedback voltage to control the transistor. The operational amplifier further includes an input stage and an output stage. The input stage includes amplifier inputs each for alternately receiving the reference voltage and the feedback voltage so that the input stage generates operating voltages corresponding to the reference voltage and the feedback voltage. The output stage receives the operating voltages alternately to control the transistor. A driver and a method of current regulation are also disclosed herein.

Abstract: A slope compensation circuit includes a first differential pair circuit, a current mirror unit, a first operating current generation circuit, and a transconductance compensation circuit. The first differential pair circuit is connected to a first current source and receives a pair of differential oscillation signals to generate a pair of differential currents corresponding to the differential oscillation signals. The current mirror unit is connected to the first differential pair circuit and mirrors the differential currents. The first operating current generation circuit is connected to the current mirror unit and generates a first operating current including the differential currents. The transconductance compensation circuit stabilizes a quiescent operating point of the first operating current generation circuit and receives the differential oscillation signals to generate an output current multiple times the value of the first operating current.

Abstract: A power amplifier with noise shaping function is provided. The power amplifier includes a differential mode integrator, an integration and adjustment unit and a switch unit. The differential mode integrator is used for receiving a differential mode input signal and a differential mode output signal, and outputting a differential mode first signal. The integration and adjustment unit is coupled to the differential mode integrator for receiving the first signal and an output signal and outputting a single-end mode second signal. The switch unit is used for receiving the second signal and outputting the differential mode output signal to drive the load. The present invention uses a common mode input signal instead of the single-end input signal to eliminate the common mode noise, and uses a 2nd-order (or more than that) integrating circuit instead of the conventional filter to achieve a preferred effect of reducing the off band noise.

Abstract: A frequency divider includes a transmission gate, a first inverter, a first switch circuit, a second switch circuit, and a second inverter. The transmission gate transmits a clock signal according to an inverted enable signal. The first inverter inverts the clock signal outputted from the transmission gate. The first switch circuit generates a first control signal according to the inverted clock signal and an output signal of the frequency divider. The second switch circuit generates a second control signal according to the clock signal, the inverted clock signal, and the first control signal. The second inverter inverts the second control signal to generate the output signal. The frequency of the clock signal is a multiple of the frequency of the output signal.

Abstract: A preset circuit of an audio power amplifier includes an inverter and a voltage drop device. The inverter receives an input signal to output an output signal, and includes a first switch and a second switch. The first switch is controlled with the input signal, and has a first terminal coupled to a power voltage and a second terminal for outputting the output signal. The second switch is controlled with the input signal, and has a third terminal for outputting the output signal and a fourth terminal coupled to a low reference voltage. The voltage drop device is coupled between the first terminal of the first switch and the power voltage and configured to lower the power voltage. The output signal is kept at a low level when the voltage drop device and the first switch are de-actuated due to the power voltage having a level below a first threshold.

Abstract: An LED driver includes a start-up feedback circuit, an operating feedback circuit and a multiplexer. The start-up feedback circuit has first terminals for receiving LED feedback voltages each delivered from at least one LED coupled to an output terminal for outputting an output voltage, of the LED driver, and generates a start-up feedback voltage accordingly. The operating feedback circuit has second terminals for receiving the LED feedback voltages, and generates an operating feedback voltage accordingly. The multiplexer selects the start-up feedback voltage for initial boost of the output voltage when the LED driver is initially activated, and selects the operating feedback voltage for following boost of the output voltage when the output voltage increases to a certain value.

Abstract: The present invention discloses a current mirror circuit generating an output current flowing through an output current path according to an input current flowing through an input current path. The current mirror circuit comprises a P type transistor in the output current path, an operational amplifier, and a basic circuit. The operational amplifier has a negative input coupled to a node receiving the input current, a positive input coupled to a drain of the P type transistor, and an output coupled to a gate of the P type transistor. The basic circuit comprises a first transistor in the input current path and a second transistor in the output current path. The first transistor has a gate and a drain coupled together. The second transistor has a gate coupled to the gate of the first transistor.

Abstract: An operational amplifier includes an output unit, a voltage drop element and a feedback unit. The output unit is provided for sourcing an output current to an output of the operational amplifier when operating with a power unit for providing a current being multiple times the value of the output current. The voltage drop is provided for generating a voltage drop in accordance with the output current. The feedback unit is controlled with the voltage drop generated by the voltage drop element and controls the output unit and the power unit to regulate the output current in accordance with the voltage drop.

Abstract: The invention provides a switching audio power amplifier with de-noise function, including a first comparator, a second comparator, a logic control unit, a de-noise circuit, and a bridge circuit. The first comparator and the second comparator respectively generate the first PWM signal and the second PWM signal, and then the logic control unit performs logic operation to generate a third PWM signal and a fourth PWM signal. If the pulse width of the third PWM signal (or the fourth PWM signal) is lower than a threshold, the de-noise circuit increases the pulse width of the third PWM signal or the fourth PWM signal and outputs the fifth PWM signal and the sixth PWM signal to drive the bridge circuit. Next, the bridge circuit conducts a driving current alternately flowing to and from a load according to the firth PWM signal and the sixth PWM signal.

Abstract: An LED driving circuit includes a control logic circuit, a dimming circuit and a counter. The control logic circuit is electrically coupled to an enable pin for receiving an input signal, and asserts an internal enable signal for activating the LED driving circuit. The dimming circuit is electrically coupled to the enable pin and outputs a control signal for controlling current flowing into at least one load connected to the LED driving circuit. The counter identifies the input signal based on a clock signal and asserts a detection signal for informing the control logic circuit of de-asserting the internal enable signal to de-activate lo the LED driving circuit when identifying the input signal as the enable signal being de-asserted for a predetermined period of the clock signal. A method of controlling an LED driving circuit is also disclosed herein.

Abstract: A frequency divider includes a transmission gate, a first inverter, a first switch circuit, a second switch circuit, and a second inverter. The transmission gate transmits a clock signal according to an inverted enable signal. The first inverter inverts the clock signal outputted from the transmission gate. The first switch circuit generates a first control signal according to the inverted clock signal and an output signal of the frequency divider. The second switch circuit generates a second control signal according to the clock signal, the inverted clock signal, and the first control signal. The second inverter inverts the second control signal to generate the output signal. The frequency of the clock signal is a multiple of the frequency of the output signal.

Abstract: A soft-start circuit is provided. The soft-start circuit comprises: an input stage, a pump stage, a second resistor and a capacitor. The input stage comprises a first resistor to receive an input voltage to provide a reference current at a first node. The pump stage comprises N current branches connected in parallel each comprising a current source connected to the first node and a switch to transfer the current from the current source to the second node while the switch operates in a connecting state. The switches has 2N connecting modes performed one after another to generate an output current with a gradual increment output current at the second node with 2N current levels; and the second resistor and the capacitor are connected in parallel between the second node and the ground potential to generate an output voltage with a gradual increment with 2N voltage levels according to output current.

Abstract: A semiconductor device includes a first metal region, a plurality of vias, a plurality of second metal regions, a plurality of openings and a third metal region. The first metal region conducts source/drain current. The second metal regions are electrically connected to the first metal region through the vias for conducting the source/drain current, in which each of the second metal regions is disposed in a distance from the adjacent second metal regions. The third metal region is electrically connected to the second metal regions through the openings, in which the resistance of the third metal region is smaller than the resistances of the first metal region and the second metal regions.

Abstract: A LED circuit is provided. The LED circuit comprises: an inductor, a group of LEDs, a power MOS and a switching circuit. The switching circuit comprises: an error amplifier generating an error output, a PWM, a RC circuit and a control means. The PWM generates a switching signal according to the error output to control the power MOS to charge or discharge the group of LEDs; the RC circuit comprises at least one first capacitor each comprising a switch, at least one second capacitors; and a resistive means connected in series between the first and the second capacitors and the error output. The control means generates a control signal according to the dimming signal to turn on the switches to activate the first capacitors during the active period of the dimming signal and turn off the switches to deactivate the first capacitors during the inactive period of the dimming signal.

Abstract: A delay circuit includes current sources, switches, a transistor switch, a charging unit and a comparator. Each of the switches is provided for receiving an enable signal to activate and convey one of the current sources. The transistor switch is activated for pulling down voltage of an operating node coupled to the switches. The charging unit provides an operating voltage for the operating node based on one of the current sources when the transistor switch is deactivated and one of the switches is activated to convey one of the current sources to the charging unit. The comparator is provided for comparing the operating voltage with a reference voltage.

Abstract: A low drop out linear regulator is provided. The low drop out linear regulator comprises an output PMOS, a load, a discharging circuit and an operational amplifier. The output PMOS comprises a source connected to a power supply and a drain having an output voltage and an output current. The drain is connected to a load circuit having a heavy and a light load period. The load is connected to the drain to generate a divided output voltage. The discharging circuit is connected to the drain to discharge the output current from the drain. The operational amplifier is to generate a control voltage according to the divided output voltage and a reference voltage; when the load circuit switches from the heavy to the light load period to make the divided output voltage higher than the reference voltage, the control voltage turns off the output PMOS and activates the discharging circuit.