Abstract: A heater is provided for use in conjunction with a fuel passageway, such as a cold start passageway, in an internal combustion engine in which fuel is injected into the passageway. The heater includes a tubular housing which is insertable into the passageway so that fuel flow through the passageway flows through the interior of the housing. A plurality of heater assemblies are also provided wherein each heating assembly has a capsule and at least one electrical heating element thermally coupled to its associated capsule. The capsules are secured to the housing so that the capsules are circumferentially spaced from each other around the housing. In one embodiment, the capsules are secured to an interior surface of the housing so that one surface of each capsule is open to the passageway. In a second embodiment, the capsules are secured around the outer periphery of the housing and each heating element is thermally connected to the housing.

Abstract: An EMI energy absorber for use with an electrical circuit, such as a hot wire air flow sensor, which has at least one electrical element which exhibits antenna characteristics at a predetermined frequency range for the EMI. The energy absorber includes a component, such as a ferrite bead, which is electrically connected in series with the element of the electrical circuit. This component exhibits a resistance which varies as a function of frequency and has a maximum resistance within the predetermined frequency range. Thus, the component functions to absorb the EMI and dissipate the EMI as heat.

Abstract: Methods and apparatus for implementing a reduced cost HDTV/SDTV video decoder are disclosed. The described joint video decoder is capable of decoding HDTV pictures at approximately the resolution of standard definition television pictures and can be used to decode HDTV and/or SDTV pictures. The described video decoder may be used as part of a picture-in-picture decoder circuit for providing picture-in-picture capability without providing multiple full resolution video decoders. The reduction in decoder circuit complexity is achieved through the use of a plurality of data reduction techniques including the use of a preparser, downsampling, and truncating pixel values.

Abstract: A novel structure and method are taught for fully discharging a capacitor and thereby reducing the capacitance needed to achieve a desired RC time constant. The invention overcomes the previously encountered problem of using a large and area-inefficient capacitor. The invention allows for conservation of integrated circuit space and is cost effective.

Abstract: A receiver arranged to receive and store broadcast data transported by elementary stream of a multiplexed and modulated digital television signal in a rewritable memory during a low power consumption mode for later recall by a user of the receiver. For recall, the receiver is fully energized, and the receiver is further arranged to transfer the broadcast data stored in the rewritable memory to a receiver storage device for further processing of the data under control of the user.

Abstract: Methods and apparatus for automatically generating a set partition adjustment renormalization rate (SPARR) threshold used to determine correct or incorrect set partition synchronization in a trellis decoder as a function of a renormalization rate are described. The invention makes use of the inventor's observation that when the system is properly synchronized, the rate of growth of cumulative error sums closely corresponds to an accumulation of minimum set partition errors. In accordance with the present invention a dummy accumulator is set up to accumulate the minimum set partition error for each symbol. If decoder set partition selection is correct the renormalization rate for the dummy accumulator will be approximately the same as an accumulator set up for the normal operation.

Abstract: Methods and apparatus for implementing a reduced cost HDTV/SDTV video decoder are disclosed. The described joint video decoder is capable of decoding HDTV pictures at approximately the resolution of standard definition television pictures and can be used to decode HDTV and/or SDTV pictures. The described video decoder may be used as part of a picture-in-picture decoder circuit for providing picture-in-picture capability without providing multiple full resolution video decoders. The reduction in decoder circuit complexity is achieved through the use of a plurality of data reduction techniques including the use of a preparser, downsampling, and truncating pixel values.

Abstract: Methods and apparatus for reducing the total amount of memory required to implement a video decoder and to perform a scan conversion operation on decoded video are described. In accordance with the present invention this is accomplished by having an interlaced to progressive (I-P) conversion circuit utilize the same frame memory used to decode the images upon which a conversion operation is performed. In this manner, the images, e.g., frames, which are buffered in the decoder are utilized by both the decoder and I-P conversion circuit thereby eliminating the need for the I-P conversion circuit to be supported with an independent frame memory. Data included in a decoder's frame memories is used to detect moving image areas for purposes of the I-P conversion process. In a specific exemplary embodiment, one of three frames, which is nearest to a present frame, is referred for calculating frame difference signals. Both subsequent and preceding frames are used to detect motion for I-P conversion purposes.

Abstract: A sample stream having a fixed sampling rate, representing a filtered version of an input symbol stream is produced by a pulse shaping and resampling device of the present invention. The pulse shaping/resampling device can be used as part of a digital modulator. In order to accommodate a wide range of (“variable”) input baud rates, as part of the pulse shaping/resampling device, a filter having an integral upsampling ratio is used, followed by a resampler circuit having a finely adjustable resampling ratio. The resampler provides an average output rate equal to the desired fixed sampling rate. In various embodiments it is followed by a buffer, which smoothes the output to provide a uniform output rate equal to the desired fixed sampling rate. The pulse shaping/resampling circuit of the present invention may be used in place of a known pulse shaping circuit in a modulator to produce a modulator capable of supporting a wide range of input signal rates.

Abstract: An improved SR latch has a two stages. A generation block generates Q and {overscore (Q)} signals from a set signal and a reset signal. The generation block also has an inactive state. A storage block receives the Q and {overscore (Q)} signals and maintains the Q signal and {overscore (Q)} signals at the voltage level that was output by the generation block prior to when the generation block blocks becomes inactive. In another embodiment, an improved D flip-flop has a sensing block with the improved SR latch of the present invention.

Abstract: Methods and apparatus for processing data representing multiple image sequences, e.g., TV programs, and displaying multiple images from different video sequences in different windows of a single display screen are disclosed. The amount of system resources required to process and display the image data are a function of the size of the windows in which the images are displayed. In accordance with the present invention demand for system resources is assessed and compared to the amount of available system resources. If the demand for system resources will exceed the available system resources, the size of one or more of the windows used to display secondary images, e.g., the small PIP windows, is reduced to reduce the burden, e.g., processing or bus bandwidth burden, on one or more system resources. In one embodiment, the system suggests a set of window sizes to the user which will allow for the decoding and display of programs without exceeding the available system resources.

Abstract: Methods and apparatus for efficiently implementing weighted median filters are described. In a first hardware embodiment, the median filter is implemented using a number of storage locations which is equal to or greater than the sum of the weight values used to implement the filtering operation. In other embodiments, the number of storage locations required to store data values is reduced to equal or approximately equal the number of data values, used in the filtering operation. In such embodiments, the data values are sorted according to size and a filter weight is associated with each data value, e.g., as part of a data record created for each one of the data values. The data value to output, as the result of the filtering operation, is determined from the stored weight values.

Abstract: The present invention is directed to a data mining method and apparatus that dynamically initiates the counting of sets of items (itemsets) at any time during the pass over the records of a database and terminates the counting at the same location in the next pass. In this manner, the present invention begins to count itemsets early and finishes counting early while keeping the number of different itemsets which are being counted in any pass relatively low.

Abstract: Methods and apparatus for implementing single instruction multiple data (SIMD) signal processing operations are described. The apparatus of the present invention include new registers and register arrays which allow data to be accessed at a word as well as sub-word or sub-register level. The registers and register arrays of the present invention may be used when implementing a system based on a SIMD architecture. Registers implemented in accordance with the present invention include a plurality of pass gates that allow an entire n-bit word stored in the register to be accessed and output as a single word or for a sub-word portion of a stored word to be accessed and output. During standard operation the registers are accessed on a word basis. However, during column access operations, e.g., when performing a transpose operation, access is performed on a sub-word basis.

Abstract: The present invention discloses a data mining method and apparatus that assigns weight values to items and/or transactions based on the value to the user, thereby resulting in association rules of greater importance. A conservative method, aggressive method, or a combination of the two can be used when generating supersets.

Abstract: Methods and apparatus for implementing a reduced cost HDTV/SDTV video decoder are disclosed. The described joint video decoder is capable of decoding HDTV pictures at approximately the resolution of standard definition television pictures and can be used to decode HDTV and/or SDTV pictures. The described video decoder may be used as part of a picture-in-picture decoder circuit for providing picture-in-picture capability without providing multiple full resolution video decoders. The reduction in decoder circuit complexity is achieved through the use of a plurality of data reduction techniques including the use of a preparser, downsampling, and truncating pixel values.

Abstract: Methods and apparatus for improving the quality of images generated by reduced resolution video decoders and new and improved video decoders which produce reduced resolution images are described. Methods and apparatus for identifying conditions within an image which may significantly degrade image quality if particular portions of the image are used by a reduced resolution decoder as reference data are described. In particular, techniques for identifying blocks of pixels, referred to as constant block regions, having approximately the same intensity in terms of luminance values, are discussed. High contrast vertical and/or horizontal edges will cause significant prediction errors in images generated by reduced resolution decoders under certain conditions. Methods for assessing when such conditions exist and a significant prediction error is likely to occur are described. In addition methods and apparatus for minimizing the effect of such prediction errors in downsampling decoders are also described.

Abstract: Methods and apparatus for implementing video decoders at a reduced cost are described. The methods include data reduction techniques, simplified inverse quantization techniques, and dynamically varying the complexity of image enhancement operations, e.g., prediction filtering operations, as a function of whether luminance or chrominance data is being processed. In order to reduce data storage requirements, luminance and chrominance data corresponding to previously encoded images may be stored at different resolutions with, in some embodiments, chrominance data being stored at less than half the resolution of luminance data. In various embodiments, data representing portions of B frames which will not be displayed is identified and discarded, e.g., without performing a decoding operation thereon. Portions of I and P frames which will not be displayed are identified and decoded at a reduced resolution and/or using simplified inverse quantization techniques.

Abstract: An implementation efficient video decoder suitable for use as a picture in picture decoder is described. In one embodiment, the video decoder receives primary and secondary bitstreams with the secondary bitstream including the video data intended to be displayed as inset pictures. The decoder uses many of the same circuit components on a time shared basis to decode both the main and inset pictures reducing the amount of circuitry required to implement the decoder. In one embodiment a preparser discards the majority of DCT coefficients in the secondary bitstream and the remaining data is variable length decoded and then variable length encoded using a non-MPEG compliant coding scheme prior to storing the inset picture data in a coded data buffer. Re-encoding of the selected inset picture data in this manner greatly reduces data storage requirements and simplifies the circuitry required to subsequently decode the inset picture data.

Abstract: Methods and apparatus for combining linear image post-processing operations with an inverse discrete cosine transform (IDCT) operation are described. In accordance with various embodiments of the present invention IDCT and downsampling operations are combined into a single operation to achieve the same image processing result as sequential IDCT and downsampling operations. By combining the two operations and performing downsampling in the DCT, as opposed to pixel domain, significant complexity reduction is achieved over embodiments where the two operations are performed sequentially. In one particular embodiment, when interlaced images are being processed, combined IDCT/downsampling circuits which perform field based, as opposed to frame based, downsampling in the DCT domain are employed. The method and apparatus of the present invention can be used to implement circuits which perform a combined full order IDCT/downsampling operation and/or a reduced complexity combined full order IDCT/downsampling operation.