Abstract: A parallel computer system includes a plurality of processor units, a data transfer network for interconnecting the processor units, a synchronizing network for allowing program execution to be performed synchronously by the individual processor units, a connecting unit for connecting the individual processor units and the synchronizing network, and an input unit connected to the synchronizing network. The connecting unit connects selectively the individual processor units to the synchronizing network in accordance with information inputted via the input unit. With the parallel computer system, a program can be executed synchronously in parallel by using a desired number of processor units of those incorporated in the system, whereby availability of processor resources of the system can be enhanced.

Abstract: Between an external terminal and the gate of one of output MOSFETs whose source or drain is connected to the external terminal, there is connected a P-channel type first protective MOSFET whose gate is connected to a high voltage side power supply terminal and which has a channel length equal to or larger than that of the output MOSFET, or an N-channel type second protective MOSFET whose gate is connected to a low voltage side power supply terminal and which has a channel length equal to or larger then that of the output MOSFET. When the external terminal is discharged by device charge, one of the protective MOSFETs is turned on, and the charge on the gate side of the output MOSFET can be likewise released by device charge to prevent ESD (Electro-Static Discharge) breakdown.

Abstract: A cell multiplexer includes a multiplexing unit for time-divisionally multiplexing ATM cell signals given from a plurality of input lines, a write controller for storing cell signals outputted from the multiplexing unit in a buffer memory successively correspondingly to the input lines, a read controller for reading the cell signals stored in the buffer memory from the buffer memory in the form of data blocks synchronized with an ATM cell structure, and a cell delineation controller for detecting delineation states of the data blocks read out from the buffer memory, notifying the read controller of delineation control information corresponding to a result of the detection and transmitting data blocks read out in synchronism with a predetermined cell structure to the output line selectively, wherein the read controller determines the read beginning addresses of data blocks to be read out nextly correspondingly to the input lines on the basis of the delineation control information notified by the cell delineati

Abstract: Parallel processors communicate with each other over a network by transmitting messages that include destination processor information. A message controller for each processor in the network receives the messages and checks for faults in the message, particularly in the destination processor number contained in a first word of the message. If a fault occurs in the destination processor number, then the faulty message is transmitted to an appropriate processor for handling the fault. In this way the network operation is not suspended because of the fault and the message is not left in the network as a result of the error occurring in the destination processor number. The processor to which the faulty message is directed is determined by a substitute destination processor number contained in the message or is predetermined and set in another way, such as by a service processor.

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacitor. The capacitor is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using a structure with decreased resistance such as silicided structure. In addition, there are made common the processing for lowering the resistance of the gate electrode of the transfer MISFETs and the processing for forming the local wiring lines.

Abstract: A microcomputer that is easy to use and connected direct to such memories as dynamic and static RAM's and to other peripheral circuits. The microcomputer has strobe signal output terminals CASH*, CASL* and RAS* for direct connection to a dynamic RAM, and chip select signal output terminals CS0* through CS6* for outputting a chip select signal in parallel with the output from the strobe signal output terminals. The microcomputer further includes address output terminals for outputting a non-multiplexed or multiplexed address signal as needed, and data I/O terminals for selectively outputting the address signal to comply with a multiple-bus interface scheme.

Abstract: A semiconductor substrate of a first conductivity type has formed on its main surface a floating gate through a first gate insulating film and has further formed over the floating gate a control gate through a second gate insulating film. In one of a paired source and drain and across which there is provided the floating gate insulately above the main surface of the substrate, a semiconductor region of second conductivity type having a lower impurity concentration than that of the paired source and drain is formed in a portion of the substrate overlapping the floating gate.

Abstract: An improvement in conditions that protective functions of an insulated gate semiconductor device with a protection circuit incorporated therein are performed, an improvement in the cutoff of heating, the prevention of malfunctions and an improvement in ease of usage can be achieved.The insulated gate semiconductor device of the present invention comprises a power insulated gate semiconductor element (M9), at least one MOSFET (M1 through M7) for a protection circuit, for controlling the power insulated gate semiconductor element, a constant-voltage circuit using forward voltages developed across diodes (D2a through D2f) for the constant-voltage circuit, and voltage restricting diodes (D1 and D0a through D0d) for controlling the upper limit of a power supply voltage of the constant-voltage circuit. Power to be supplied to the voltage restricting diodes is supplied from an external gate terminal of the power insulated gate semiconductor element.

Abstract: Between an external terminal and the gate of one of output MOSFETs whose source or drain is connected to the external terminal, there is connected a P-channel type first protective MOSFET whose gate is connected to a high voltage side power supply terminal and which has a channel length equal to or larger than that of the output MOSFET, or an N-channel type second protective MOSFET whose gate is connected to a low voltage side power supply terminal and which has a channel length equal to or larger then that of the output MOSFET. When the external terminal is discharged by device charge, one of the protective MOSFETs is turned on, and the charge on the gate side of the output MOSFET can be likewise released by device charge to prevent ESD (Electro-Static Discharge) breakdown.

Abstract: An increase in the GND resistance and a drop in the resistance against electromigration are minimized when the ground voltage lines for shunting are finely constituted by using an Al wiring of the same layer as the pad layer, owing to the employment of a layout in which the arrangement of connection holes 24, 26 in a pad layer connected to one (data line) of the complementary data lines and the arrangement of connection holes in a pad layer connected to the other one (data line bar) of the complementary data lines, are inverted from each other every two bits of memory cells in the SRAM along the direction in which the complementary data lines extend.

Abstract: A defect remedy LSI mounted on a memory module, comprising: an input interface portion for capturing address and control signals, the input interface portion being the same as that of a dynamic RAM; an input/output interface portion corresponding to a data bus of a memory device comprised of a plurality of dynamic random access memories; a memory circuit to which a chip address and an X defective address of any of the plurality of random access memories are electrically written, the memory circuit being substantially made nonvolatile; a redundancy remedy RAM portion composed of a static RAM wherein a word line is selected by a compare match signal between an X address signal and the defective address of the memory circuit, the X address signal and the defective address being captured via the input interface portion, and a column is selected by a Y address signal captured via the input interface portion; a selecting portion for connecting a data input/output bus of the redundancy remedy RAM portion to an input

Abstract: A semiconductor memory incorporating an operation circuit for carrying out logical operations on data and arithmetic operations on address signals. The memory is arranged functionally so that the data representing the result of each of such operations is written to a memory array while also being output through an external terminal in the same memory cycle.

Abstract: A batch erasable nonvolatile memory device and an apparatus using the same provided with memory cells which are adapted to execute an erase operation by a ejecting an electric charge accumulated at floating gates by program operation (including a pre-write operation), carries out, in sequence, a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvolatile memory cells

Abstract: A semiconductor integrated circuit is provided which includes a charge pump circuit for forming a step-up (boost) voltage higher than a desired internal voltage, a voltage dividing circuit which forms a plurality of divided voltages based on a reference voltage, and a control circuit which intermittently operates the charge pump circuit so that an output voltage of the charge pump circuit provides the desired internal voltage obtained by adding a voltage obtained by multiplying a particular voltage among the plurality of divided voltages by n to a predetermined divided voltage.

Abstract: A semiconductor substrate of a first conductivity type has formed on its main surface a floating gate through a first gate insulating film and has further formed over the floating gate a control gate through a second gate insulating film. In one of a paired source and drain and across which there is provided the floating gate insulatedly above the main surface of the substrate, a semiconductor region of second conductivity type having a lower impurity concentration than that of the paired source and drain is formed in a portion of the substrate overlapping the floating gate.

Abstract: A semiconductor memory device having a plurality of nonvolatile memory devices or elements disposed in a matrix arrangement as one or more memory arrays is provided with a write operation and a verify mode which is automatically implemented when the write operation of the memory device ends. In connection with this, an auto-verify function is set in an internal circuit associated with the memory in accordance with a predetermined control signal and wherein a read mode subsequent to the write operation is implemented. During the auto-verify function, the read mode is implemented by effecting a data comparison circuit, such as an exclusive-OR logic circuit, which performs a coincidence/non-coincidence operation comparing the write data and the read data.

Abstract: A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data.

Abstract: For taking a characteristic impedance matching of signal transmission lines in a package which carries thereon a semiconductor chip with a very high-speed LSI formed thereon, there is provided a semiconductor integrated circuit device wherein one ends of signal transmission lines formed on a main surface of a package substrate are extended up to the position just under pads formed on a main surface of the semiconductor chip and are connected to the pads on the chip electrically through bump electrodes, while opposite ends of the signal transmission lines are extended to the outer peripheral portion of the main surface of the package substrate and outer leads are bonded thereto.

Abstract: An ATM exchanger includes a plurality of switch units connected in multiple stages, in which a circuit is provided for writing a test cell pattern into and reading it from a buffer memory of each switch unit in accordance with an instruction from a controller, so that the test cell read from the buffer memory can be transferred appropriately to the controller.

Abstract: In depositing a silicon oxide film which constitutes part of a final passivation film onto a bonding pad formed on an interlayer insulating film, the silicon oxide depositing step is divided in two stages, and after the first deposition, the bonding pad is once exposed by etching, then the second deposition is performed, whereby the silicon oxide film which has thus been deposited in two stages is formed over a fuse element formed under the interlayer insulating film, while on the bonding pad is formed only the silicon oxide film deposited in the second stage. As a result, at the time of etching polyimide resin, silicon nitride film and silicon oxide film successively to expose the bonding pad, there remains a sufficient thickness of insulating film between the bottom of an aperture which is formed at the same time and the fuse element. Thereafter, an electrical test is conducted while applying a probe to the bonding pad and, where required, the fuse element located under the aperture is cut.