Patents Assigned to HSIO TECHNOLOGIES, LLC
  • Publication number: 20120055702
    Abstract: A compliant printed flexible circuit including a flexible polymeric film and at least one dielectric layer bonded to the polymeric film with recesses corresponding to a target circuit geometry. A conductive material is printed in at least a portion of the recesses to form a circuit geometry. At least one dielectric covering layer is printed over at least the circuit geometry. Openings can be printed in the dielectric covering layer to provide access to at least a portion of the circuit geometry.
    Type: Application
    Filed: May 27, 2010
    Publication date: March 8, 2012
    Applicant: HSIO TECHNOLOGIES, LLC
    Inventor: James Rathburn
  • Publication number: 20120049877
    Abstract: A test socket that provides a temporary interconnect between terminals on an integrated circuit (IC) device and contact pads on a test printed circuit board (PCB). The test socket includes a compliant printed circuit and a socket housing. The compliant printed circuit includes at least one compliant layer, a plurality of first contact members located along a first major surface, a plurality of second contact members located along a second major surface, and a plurality of conductive traces electrically coupling the first and second contact members. The compliant layer is positioned to bias the first contact members against the terminals on the IC device and the second contact members against contact pads on the test PCB. The socket housing is coupled to the compliant printed circuit so the first contact members are positioned in a recess of the socket housing sized to receive the IC device.
    Type: Application
    Filed: May 27, 2010
    Publication date: March 1, 2012
    Applicant: HSIO TECHNOLOGIES, LLC
    Inventor: James Rathburn
  • Publication number: 20120049342
    Abstract: A method of making semiconductor die terminals and a semiconductor device with die terminals made according to the present method. At least a first mask layer is selectively printed on at least a portion of a wafer containing a plurality of the semiconductor devices to create first recesses aligned with electrical terminals on the semiconductor devices. A conductive material is deposited in a plurality of the first recesses to form die terminals on the semiconductor devices. The first mask layer is removed to expose the die terminals, and the wafer is diced into a plurality of discrete semiconductor devices.
    Type: Application
    Filed: June 15, 2010
    Publication date: March 1, 2012
    Applicant: HSIO TECHNOLOGIES, LLC
    Inventor: James Rathburn
  • Publication number: 20120051016
    Abstract: A semiconductor socket including a substrate with a plurality of through holes extending from a first surface to a second surface. A plurality of discrete contact members are located in the plurality of the through holes. The plurality of contact members each include a proximal end accessible from the second surface, and a distal end extending above the first surface. At least one dielectric layer is bonded to the second surface of the substrate with recesses corresponding to target circuit geometry. A conductive material deposited in at least a portion of the recesses to form conductive traces redistributing terminal pitch of the proximal ends of the contact members.
    Type: Application
    Filed: June 15, 2010
    Publication date: March 1, 2012
    Applicant: HSIO TECHNOLOGIES, LLC
    Inventor: James Rathburn
  • Publication number: 20120043119
    Abstract: An array of composite polymer-metal contact members adapted to form solder free electrical connections with a first circuit member. The contact members include a resilient polymeric base layer and an array of metalized traces printed on selected portions of the base layer. Conductive plating is applied to the metalized layer to create an array of conductive paths. The resilient polymeric base layer, the metalized layer, and the conductive plating have an aggregate spring constant sufficient to maintain distal portions of the contact members in a cantilevered configuration and to form a stable electrical connection between the distal portions and the first circuit member solely by compressive engagement.
    Type: Application
    Filed: May 27, 2010
    Publication date: February 23, 2012
    Applicant: HSIO TECHNOLOGIES, LLC
    Inventor: James Rathburn
  • Publication number: 20120044659
    Abstract: A compliant printed circuit semiconductor package including a compliant printed circuit with at least a first dielectric layer selectively printed on a substrate with first recesses. A conductive material is printed in the first recesses to form contact members accessible along a first surface of the compliant printed circuit. At least one semiconductor device is located proximate the first surface of the compliant printed circuit. Wirebonds electrically couple terminals on the semiconductor device to the contact members. Overmolding material seals the semiconductor device and the wirebonds to the first surface of the compliant printed circuit. Contact pads on a second surface of the compliant printed circuit are electrically coupled to the contact members.
    Type: Application
    Filed: May 25, 2010
    Publication date: February 23, 2012
    Applicant: HSIO TECHNOLOGIES, LLC
    Inventor: James Rathburn
  • Publication number: 20120043130
    Abstract: An interconnect assembly including a resilient material with a plurality of through holes extending from a first surface to a second surface. A plurality of discrete, free-flowing conductive particles is located in the through holes. The conductive particles are preferably substantially free of non-conductive materials. A plurality of first contact tips are located in the through holes adjacent the first surface and a plurality of second contact tips are located in the through holes adjacent the second surface. The resilient material provides the required resilience, while the conductive particles provide a conductive path substantially free of non-conductive materials.
    Type: Application
    Filed: May 27, 2010
    Publication date: February 23, 2012
    Applicant: HSIO TECHNOLOGIES, LLC
    Inventor: James Rathburn
  • Publication number: 20120043667
    Abstract: A package for at least one semiconductor device and a method for making the package. At least one dielectric layer is selectively printed on at least a portion of the semiconductor device creating first recesses aligned with a plurality of the electrical terminals. A conductive material is printed in the first recesses forming contact members on the semiconductor device. At least one dielectric layer is selectively printed on at least a portion of the package to create a plurality of second recesses corresponding to a target circuit geometry. A conductive material is printed in at least a portion of the second recesses to create a circuit geometry. The circuit geometry includes a plurality of exposed terminals electrically coupled to the electric terminals on the semiconductor device.
    Type: Application
    Filed: May 27, 2010
    Publication date: February 23, 2012
    Applicant: HSIO TECHNOLOGIES, LLC
    Inventor: James Rathburn