Abstract: An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.

Abstract: Probes are electrically connected to a surface of a tunnel junction film stack comprising a free layer, a tunnel barrier, and a pinned layer. Resistances are determined for a variety of probe spacings and for a number of magnetizations of one of the layers of the stack. The probe spacings are a distance from a length scale, which is related to the Resistance-Area (RA) product of the tunnel junction film stack. Spacings from as small as possible to about 40 times the length scale are used. Beneficially, the smallest spacing between probes used during a resistance measurement is under 100 microns. A measured in-plane MagnetoResistance (MR) curve is determined from the “high” and “low” resistances that occur at the two magnetizations of this layer. The RA product, resistances per square of the free and pinned layers, and perpendicular MR are determined through curve fitting.

Abstract: One embodiment relates to a sensing system that includes a magnetic encoder wheel having alternating pole magnetic domains along a circumference thereof. The magnetic encoder wheel is configured to rotate about a first axis. The sensing system further includes a magnetic field sensing element in spatial relationship with the magnetic encoder wheel that is oriented to sense magnetic field components extending generally in a direction parallel to a second axis that is perpendicular to the first axis. The sensing system also includes a magnetic flux influencing element configured to influence magnetic field components associated with the alternating pole magnetic domains of the magnetic encoder to reduce magnetic field components associated with the first axis.

Abstract: Probes are electrically connected to a surface of a tunnel junction film stack comprising a free layer, a tunnel barrier, and a pinned layer. Resistances are determined for a variety of probe spacings and for a number of magnetizations of one of the layers of the stack. The probe spacings are a distance from a length scale, which is related to the Resistance-Area (RA) product of the tunnel junction film stack. Spacings from as small as possible to about 40 times the length scale are used. Beneficially, the smallest spacing between probes used during a resistance measurement is under 100 microns. A measured in-plane MagnetoResistance (MR) curve is determined from the “high” and “low” resistances that occur at the two magnetizations of this layer. The RA product, resistances per square of the free and pinned layers, and perpendicular MR are determined through curve fitting.

Abstract: Probes are electrically connected to a surface of a tunnel junction film stack comprising a free layer, a tunnel barrier, and a pinned layer. Resistances are determined for a variety of probe spacings and for a number of magnetizations of one of the layers of the stack. The probe spacings are a distance from a length scale, which is related to the Resistance-Area (RA) product of the tunnel junction film stack. Spacings from as small as possible to about 40 times the length scale are used. Beneficially, the smallest spacing between probes used during a resistance measurement is under 100 microns. A measured in-plane MagnetoResistance (MR) curve is determined from the “high” and “low” resistances that occur at the two magnetizations of this layer. The RA product, resistances per square of the free and pinned layers, and perpendicular MR are determined through curve fitting.

Abstract: An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.

Abstract: A semiconductor package includes a curved body and a plurality of semiconductor die. The curved body includes first and second opposing end regions and an intermediate center region. The curved body has a first inflection point at the center region, a second inflection point at the first end region and a third inflection point at the second end region. The center region has a convex curvature with a minimal extremum at the first inflection point, the first end region has a concave curvature with a maximal extremum at the second inflection point and the second end region has a concave curvature with a maximal extremum at the third inflection point. The plurality of semiconductor die are attached to an upper surface of the curved body between the maximal extrema.

Abstract: A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC1 solution and excess surface portions of the SiGe region are selectively removed. The SC1 etching process can be part of a rework method in which overgrowth regions of SiGe are selectively removed by exposing the SiGe to and SC1 solution maintained at an elevated temperature. The etching process is carried out for a period of time sufficient to remove excess surface portions of SiGe. The SC1 etching process can be carried out at elevated temperatures ranging from about 25° C. to about 65° C.

Abstract: Some aspects of the present disclosure relate to techniques for measuring an angular position of a rotating shaft. As will be described in greater detail below, some angle measurement systems of the present disclosure include at least two magnets that cooperatively rotate at different rates according to a predetermined relationship (e.g., a predetermined gear ratio). Two or more magnetic field sensing elements, which are often stationary, measure the directionality of the resultant magnetic field at different positions for a particular angular shaft position. Based on the directionality measured by the magnetic field sensing elements, the techniques can determine an absolute angular position of the rotating shaft, which can be greater than three-hundred and sixty degrees.

Abstract: An RF semiconductor package includes a substrate having generally planar top and bottom surfaces. The substrate includes a metallic base region and one or more metallic signal terminal regions extending from the top surface to the bottom surface, and an insulative material separating the metallic regions from one another. The bottom surface of an RF semiconductor die is surface-mounted to the base region at the top substrate surface. The RF semiconductor die has a terminal pad disposed at a top surface of the RF semiconductor die. The terminal pad is electrically connected to one of the signal terminal regions at the top substrate surface. A lid is attached to the top substrate surface so that the RF semiconductor die is enclosed by the lid to form an open-cavity around the RF semiconductor die. The base and signal terminal regions are configured for surface-mounting at the bottom substrate surface.

Abstract: A phase change memory device and a method for programming the same. The method includes determining a characterized lowest SET current and corresponding SET resistance for the phase change memory device. The method includes determining a characterized RESET current slope for the phase change memory device. The method also includes calculating a first current amplitude for a RESET pulse based on the characterized lowest SET current and the characterized RESET current slope. The method includes applying the RESET pulse to a target memory cell in the phase change memory device and measuring the resistance of the target memory cell. If the measured resistance is substantially less than a target resistance, the method further includes applying one or more additional RESET pulses. In one embodiment of the invention, the one or more additional RESET pulses have current amplitudes greater than a previously applied RESET pulse.

Abstract: Various illustrative embodiments of methods for manufacturing a semiconductor device are described. These methods may include, for example, forming a first polysilicon layer above a substrate, wherein the first polysilicon layer comprises a doped portion, and forming a second polysilicon layer over a surface of the first polysilicon layer. Also, various illustrative embodiments of semiconductor devices are described that may be manufactured such as by the various methods described herein.

Abstract: An air cavity package is manufactured by attaching a die to a surface of a copper heat sink, dispensing a bead of epoxy around a periphery of the heat sink surface after the die is attached to the copper heat sink so that the bead of epoxy generally surrounds the die and placing a ceramic window frame on the bead of epoxy. The epoxy is cured to attach a bottom surface of the ceramic window frame to the copper heat sink.

Abstract: Embodiments of the present invention provide a method of forming a conductive stud contacting a semiconductor device. The method includes forming a protective layer covering the semiconductor device; selectively etching an opening down through the protective layer reaching a contact area of the semiconductor device, the opening being away from a protected area of the semiconductor device; and filling the opening with a conductive material to form the conductive stud. One embodiment may further include forming a dielectric liner directly on top of the semiconductor device, and forming the protective layer on top of the dielectric liner. Embodiments of the present invention also provide a semiconductor device made thereof.

Abstract: Methods of forming integrated circuit devices according to embodiments of the present invention include forming a PMOS transistor having P-type source and drain regions, in a semiconductor substrate, and then forming a diffusion barrier layer on the source and drain regions. A silicon nitride layer is deposited on at least portions of the diffusion barrier layer that extend opposite the source and drain regions. Hydrogen is removed from the deposited silicon nitride layer by exposing the silicon nitride layer to ultraviolet (UV) radiation. This removal of hydrogen may operate to increase a tensile stress in a channel region of the field effect transistor. This UV radiation step may be followed by patterning the first and second silicon nitride layers to expose the source and drain regions and then forming silicide contact layers directly on the exposed source and drain regions.

Abstract: An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transistors. Fluorine is implanted into the opening to form an epitaxial fluorine-doped semiconductor layer and an underlying fluorine-doped semiconductor layer in the first area. A composite gate stack including a high-k gate dielectric layer and an adjustment oxide layer is formed in the first and second area. P-type and n-type field effect transistors (FET's) are formed in the first and second areas, respectively. The epitaxial fluorine-doped semiconductor layer and the underlying fluorine-doped semiconductor layer compensate for the reduction of the decrease in the threshold voltage in the p-FET by the adjustment oxide portion directly above.

Abstract: According to an embodiment of a high power package, the package includes a copper heat sink, a ceramic lead frame and a semiconductor chip. The copper heat sink has a thermal conductivity of at least 350 W/m K. The ceramic lead frame is attached to the copper heat sink with an epoxy. The semiconductor chip is attached to the copper heat sink on the same side as the lead frame with an electrically conductive material having a melting point of about 280° C. or greater.

Abstract: A second photoresist having a second photosensitivity is formed on a substrate. A first photoresist having a first photosensitivity, which is greater than second photosensitivity, is formed on the second photoresist. Preferably, the first photoresist is a gray resist that becomes transparent upon exposure. At least one portion of the first photoresist is lithographically exposed employing a first reticle having a first pattern to form at least one transparent lithographically exposed resist portion, while the second photoresist remains intact. The second photoresist is lithographically exposed employing a second reticle including a second pattern to form a plurality of lithographically exposed shapes in the second photoresist. The plurality of lithographically exposed shapes have a composite pattern which is the derived from the second pattern by limiting the second pattern only within the area of the at least one transparent lithographically exposed resist pattern.

Abstract: One embodiment relates to a method for communicating over a transmission medium shared between a plurality of nodes including a source node, a proxy node, and other nodes. In the method, a transmission data unit is transmitted from the source node to the proxy node and to the other nodes. A confirmation is selectively transmitted from the proxy node to the other nodes based on whether a reception data unit corresponding to the transmission data unit is correctly received at the proxy node. Based on whether the confirmation is received at one of the other nodes, a negative acknowledgement is selectively transmitted from the one of the other nodes to the source node. Other methods and devices are also disclosed.

Abstract: According to an embodiment, a mixed signal controller includes a fine controller, a coarse controller and a digital controller. The fine controller is operable to output an analog modulation signal responsive to an analog control signal and a voltage signal input to the fine controller. The coarse controller is operable to output a digital pulse width modulation (PWM) signal responsive to the analog modulation signal and an analog PWM reference signal input to the coarse controller. The digital controller is operable to program the analog control signal and the analog PWM reference signal responsive to the digital PWM signal so that the fine and coarse controllers together regulate the voltage signal at a predetermined voltage level.