Abstract: According to one embodiment, a power transistor package includes an electrically conductive flange configured to be connected to a source of a power transistor device. The package further includes a first terminal mechanically fastened to the flange and configured to be electrically connected to a gate of the power transistor device and a second terminal mechanically fastened to the flange and configured to be electrically connected to a drain of the power transistor device. The package also includes a bus bar mechanically fastened to the flange which extends between and connects at least two different DC bias terminals mechanically fastened to the flange. The bus bar is configured to be electrically connected to the drain via one or more RF grounded connections.

Abstract: Embodiments of the present invention provide a method of placing printing assist features in a mask layout. The method includes providing a design layout having one or more designed features; generating a set of parameters, the set of parameters being associated with one or more printing assist features (PrAFs); adding the one or more PrAFs of the set of parameters to the design layout to produce a modified design layout; performing simulation of the one or more PrAFs and the one or more designed features on the modified design layout; verifying whether the one or more PrAFs are removable based on results of the simulation; and creating a set of PrAF placement rules based on the set of parameters, if the one or more PrAFs are verified as removable. The set of PrAF placement rules may be used in creating a final set of PrAF features to be used for creating the mask layout.

Abstract: Embodiments of the present invention provide a method for making mask shape adjustment The method includes creating a first mask shape; identifying one or more mask segments of the first mask shape as candidate mask segments of needing segment adjustment; applying an optical proximity correction (OPC) process to the first mask shape, the OPC process identifying at least one of the candidate mask segments as a constrained mask segment; applying a rotational adjustment to the constrained mask segment; and creating a second mask shape having the constrained mask segment being rotationally adjusted. A system and a machine-readable medium for performing the above method are also provided.

Abstract: According to one embodiment, an electronic package includes a semiconductor die, a heat sink and a metallization layer interposed between the semiconductor die and the heat sink. The metallization layer attaches the semiconductor die to the heat sink. The metallization layer has a thickness of about 5 ?m or less and a thermal conductivity of about 60 W/m·K or greater.

Abstract: A method for controlling etching during photolithography in the fabrication of an integrated circuit in connection with first and second features that are formed on the integrated circuit having a gap there between comprising depositing a layer of photoresist on the integrated circuit, selectively exposing portions of the photoresist through at least one photolithography mask having a pattern including means for alleviating line end shortening of the first and second lines adjacent the gap, and developing the photoresist after the selective exposing step.

Abstract: An integrated circuit that includes a substrate having first and second active regions is disclosed. A first transistor of a first type and a second transistor of a second type are disposed in the first and second active regions respectively. Each transistor includes a gate stack having a metal gate electrode over a gate dielectric layer. First and second gate threshold voltage adjusting (GTVA) layers contacting first and second gate dielectric layer of the first and second transistors are provided. The first GTVA layer tunes a gate threshold voltage of the first transistor. A channel of the second transistor includes dopants to tune the gate threshold voltage of the second transistor.

Abstract: According to one embodiment, a balun includes one or more transformers configured to block DC power between a line and a device at microwave frequencies. The one or more transformers block DC power between the line and the device by electromagnetically coupling the device to the line.

Abstract: According to an embodiment, a programmable logic device includes a plurality of logic blocks, memory, a plurality of connection control elements and a logic unit. The logic blocks are grouped into one or more programmed partitions. The memory stores authentication information and partition information. The connection control elements controllably interconnect different ones of the logic blocks. The logic unit controls external access to the one or more partitions based on the authentication information, controls reprogramming of the one or more partitions based on at least some of the partition information and configures the connection control elements based on at least some of the partition information.

Abstract: According to an embodiment, a programmable logic device includes a plurality of logic blocks and a logic unit. The logic blocks are grouped into one or more partitions. The logic unit controls external access to the one or more partitions, controls programming of the one or more partitions and controls interconnection and operation of the one or more partitions during operation of the programmable logic device.

Abstract: According to an embodiment, a programmable logic device includes a plurality of logic blocks, memory and a logic unit. The logic blocks are grouped into one or more partitions. The memory stores authentication and partition information uploaded to the programmable logic device prior to partition programming. The logic unit authenticates programming access to the one or more partitions based on the authentication information and controls programming of the one or more partitions based on the partition information.

Abstract: A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substrate and a lower region adjacent to the bottom of the trench; forming an oxidized layer of the substrate in the bottom region of the trench; and removing the oxidized layer of the substrate from the bottom region of the trench, a cross-sectional area of the lower region of the trench greater than a cross-sectional area of the upper region of the trench.

Abstract: A system and method for transferring information to a device include sending a first challenge from an information provider to programming equipment, and responding to the first challenge by the programming equipment. A second challenge is sent from the programming equipment to the information provider, which responds to the second challenge. Information is encrypted by the information provider and sent from the information provider to the programming equipment.

Abstract: An integrated circuit processing system is provided including a substrate having an integrated circuit; an interconnect layer over the integrated circuit; a low-K dielectric layer over the interconnect layer; a hard mask layer over the low-K dielectric layer; a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; and an interconnect metal in the via opening.

Abstract: An input/output (I/O) mixed-voltage drive circuit and electrostatic discharge protection device for coupling to an I/O pad. The device includes an NFET device having a gate, a drain, a source and body, the gate adapted for coupling to a pre-drive circuit, the source and the body being coupled to one another and to ground. The device also includes a bipolar junction transistor having a collector, an emitter and a base, the emitter being coupled to the drain of the NFET and the collector being coupled to the I/O pad.

Abstract: A method of training an Optical Proximity Correction (OPC) model comprises symmetrizing a complex design to be a test pattern having orthogonal symmetry. Symmetrizing may comprise establishing a axis of symmetry passing through the design, thereby dividing the design into two portions; deleting one of the two portions; and mirror-imaging the other of the two portions about the axis of symmetry. The design may be centered.

Abstract: One embodiment relates to a sensor. The sensor includes a first magnet having a first surface and a second magnet having a second surface. A differential sensing element extends alongside the first and second surfaces. The differential sensing element includes a first sensing element and a second sensing element. In addition, a layer of ferromagnetic or paramagnetic material runs between the first and second magnets and spaces the first and second magnets from one another. Other apparatuses and methods are also set forth.

Abstract: One embodiment relates to a method of manufacturing a magnetic sensor. In the method, an engagement surface is provided. A magnet body is formed over the engagement surface by gradually building thickness of a magnetic material. The magnet body has a magnetic flux guiding surface that substantially corresponds to the engagement surface. Other apparatuses and methods are also set forth.

Abstract: One embodiment of the present invention relates to a method for key management in a communications network. In this method, a public key authentication scheme is carried out between a security controller and a plurality of nodes to establish a plurality of node-to-security-controller (NSC) keys. The NSC keys are respectively associated with the plurality of nodes and are used for secure communication between the security controller and the respective nodes. Other methods and devices are also disclosed.

Abstract: An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; applying a hard mask layer over the low-K dielectric layer; forming a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; applying a first fluid and a second fluid in the via opening for removing an overhang of the hard mask layer; depositing an interconnect metal in the via opening; and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer.

Abstract: Probes are electrically connected to a surface of a tunnel junction film stack comprising a free layer, a tunnel barrier, and a pinned layer. Resistances are determined for a variety of probe spacings and for a number of magnetizations of one of the layers of the stack. The probe spacings are a distance from a length scale, which is related to the Resistance-Area (RA) product of the tunnel junction film stack. Spacings from as small as possible to about 40 times the length scale are used. Beneficially, the smallest spacing between probes used during a resistance measurement is under 100 microns. A measured in-plane MagnetoResistance (MR) curve is determined from the “high” and “low” resistances that occur at the two magnetizations of this layer. The RA product, resistances per square of the free and pinned layers, and perpendicular MR are determined through curve fitting.