Abstract: Targets or test structures used for measurements in semiconductor devices having long lines exceeding design rule limitations are divided into segments. In one embodiment, the segments have periodicity in a direction parallel to the length of the lines. In another embodiment, the segments of test structures in adjacent lines do not have periodicity in a direction parallel to the length of the lines. The lack of periodicity is achieved by staggering segments of substantially equal lengths in adjacent lines, or by dividing the lines into segments having unequal lengths. The test structures may be formed in scribe line regions or die regions of a semiconductor wafer.

Abstract: A process for fabricating a semiconductor device having deep trench structures includes forming a first portion of the trench in a semiconductor substrate and a second portion of the trench in a selectively-formed upper layer. After etching the substrate to form the first portion of the trench, a protective layer is deposited over the inner surface of the trench in the semiconductor substrate and the upper layer is selectively formed on a principal surface of the semiconductor substrate. During formation of the upper layer, a wall surface is formed in the upper layer that is continuous with the wall surface of the trench in the semiconductor substrate. By forming a second portion of the trench in the selectively-formed upper layer, a deep trench is produced having a high aspect ratio and well defined geometric characteristics.

Abstract: A method for monitoring precision of placement of semiconductor wafers in a semiconductor processing apparatus includes measuring thickness of an insulating film on a surface of a semiconductor substrate before etching a portion of the insulating film from the surface of the semiconductor substrate. The method further includes re-measuring the thickness of the insulating film to determine etch rates for the film at selected locations on the surface of the semiconductor wafer, and based on the determined etch rates, determining misalignment of the semiconductor wafer.

Abstract: A method and apparatus according to the present invention define optimal conditions for a scanning electron microscope (SEM), preferably a critical dimension scanning electron microscope (CDSEM). The present invention provides an image quality monitor that utilizes image processing and optimization to maintain image quality at a desired level. Images from a stage sample are automatically collected, while microscope operational parameters are determined based on image processing to enable continuous monitoring of microscope operation. The technique may be performed manually or automatically and generates set points for beam conditioning elements to produce or maintain ideal beam conditions to enhance image quality. The present invention generates data indicating optimized values for each beam alignment parameter. The optimized values are applied to the internal microscope values to optimize the beam.

Abstract: A process and method for compensating for a radial non-uniformity on a wafer that includes the steps of: centering a rotational thickness non-uniformity of a film on the wafer about the axis of the spin susceptor following a CMP process; positioning a nozzle in the spin processing unit to direct the etching solution along a radius of the wafer; adjusting the flow of the etching solution from the nozzle; adjusting the rotational speed of the spin susceptor to control the residence time of the etching solution; and coordinating the rotational speed of the spin susceptor, flow of etching solution and positioning of the nozzle to maximize the removal of material. The process may be utilized to compensate for the bowl-shaped non-uniformities of an STI oxide. These non-uniformities are compensated for and addressed after a CMP process.

Abstract: Metal residue on a semiconductor surface resulting from metal chemical mechanical polishing (“CMP”) process are eradicated using a dry clean process. The dry cleaning uniformly removes or substantially eliminates metal residue from the surface of the semiconductor. An unintended metal short that may be present due to the residue may thereby be eliminated by adjusting the dry cleaning process based on a type of dry cleaning material, and type and a thickness of the residue.

Abstract: A pattern can be projected on a resist film layer deposited on a semiconductor surface. The pattern can include structural elements having different feature sizes. Structural elements having feature sizes below a certain limit are not resolved on the resist film layer. The dimension of the corresponding resist pattern can be reduced and the difference can be related to focus parameters of the exposure tool.

Abstract: A method for a semiconductor process includes correlating yield loss for the performance of a processing step in a semiconductor manufacturing process with the mechanical placement of the semiconductor substrate and, based on the correlation, placing semiconductor substrates in a position with sufficient placement precision to reduce yield loss below a predetermined threshold.

Abstract: A method of controlling lithographic overlay offsets in the manufacture of semiconductor devices from wafers, comprising the steps of forming a lithographic pattern on a wafer layer with a lithographic tool, processing the wafer after the pattern is formed to enable fabrication of a semiconductor device, predicting overlay offset corrections based on one or more factors involved in the processing of the wafer, and utilizing the predicted overlay offset corrections to positionally control the lithographic tool.

Abstract: In a method of affecting cleaning or chamber process control to remove residues of fluorinated discharges from internal PECVD chamber hardware during manufacture of a semiconductor or integrated circuit, the improvement of removing the fluorinated discharges without opening the chamber and without causing chamber downtime, comprising: a) maximizing H-atom concentration in a gas mix of a plasma containing H2 through the use of high rf power and low pressure to obtain an in-situ H2 plasma; and b) subjecting a reactor chamber containing build-up residues from previous chamber treatment with a fluorinated plasma, with the in-situ H2 plasma from step a) without opening the chamber and without shutting down the chamber to remove the build-up residues of the fluorinated plasma.

Abstract: The disclosed system and method relates to the prediction of processing tool control parameters, i.e. controller state, for a particular processing tool, which has little or no utilization history, i.e. is data starved or has not gone through the learning curve, for a given process, or has undergone an event for which the current controller state has been reset or is otherwise now sub-optimal. The prediction is based on the processing tool control parameters of a substantially similar processing tool, being used in a substantially similar fashion to the given situation, which has significant utilization history. The processing tool having significant utilization history may be the same processing tool as the processing tool with little or no processing history where a manufacturing event disrupts the operations thereof. In this case, the pre-event control parameters and utilization history may be used, according to the disclosed embodiments, to predict the post-event controller state.

Abstract: A system and method for processing a semiconductor material out-gassing a gas including a radiant energy source arranged to expose the semiconductor material to energy to decompose the gas and a sensor to sense a parameter of processing such that the radiant energy source is controlled based upon the sensed parameter information.

Abstract: According to an embodiment of the present invention, a method is provided for determining a fail string for a device. The method includes determining a test pattern for a portion of an address space wherein the test pattern includes at least one address in the address space and the portion of the address space includes at least one x address and at least one y addresses. The method executes a test a plurality of times for each test pattern, wherein every combination of the test pattern is tested, wherein the combinations include each address held at a first potential for at least a first test and a second potential for at least a second test. The method includes determining a fail string for the device including pass/fail results for the test pattern, and combining the pass/fail results in the fail string.

Abstract: A method for testing devices produced in front end lots involving loading a plurality of front end lots into a tester without requiring the tester to complete tests on a previous front end lot. A secondary lot of devices is unloaded from the tester, the secondary lot containing devices from a plurality of front end lots. The plurality of front-end lots may form a batch. In this case, a plurality of secondary lots unloaded from the tester could correspond to the front-end lots, and could be considered to be part of the same batch. All secondary lots of the batch, except for the last secondary lot of the batch, may contain only pass devices, such that all fail devices from the batch are unloaded and then tested together, in the last secondary lot. The loading of the front-end lots may be asynchronous with the unloading of the secondary lots.

Abstract: A device to implant impurities into a semiconductor wafer has a process chamber having a wall, a pressure compensation unit, a disk to support a plurality of semiconductor wafers within the process chamber. The disk has a radially extending slot arranged among the wafers. A beam gun is positioned within the process chamber to shoot an ion beam at the semiconductor wafers. A cryo pump minimizes the pressure within the process chamber. A first ion gauge is positioned between the process chamber and the cryo pump. A second ion gauge extends through the wall of the process chamber. A switching device selectively connects the first or second ion gauge to the pressure compensation unit. A faraday receives ions from the ion gun filter after the ions travel through the slot in the disk. A current meter counts the number of electrons flowing to the disk faraday to neutralize the ions.

Abstract: A method of analyzing cells of a memory device is disclosed. Generally, a plurality of fail signatures is generated, wherein each fail signature is associated with a type of failure. Voltages according to a plurality of test patterns are applied to nodes of a cell of the memory device. Fail data of the cell for the plurality of patterns is then analyzed, and a fail signature of the cell is determined. A type of failure of the cell based upon the plurality of fail signatures is then determined. A system for analyzing cells of a memory device is also disclosed. The system generally includes a plurality of probes applying different voltages to a cell of the memory device. A control circuit varies the voltages applied to the cell, and compares the failures of the cell as the test voltage applied to the cell is varied to an artificial bit map. Finally, an output device generates an output indicating a type of failure of the cell.

Abstract: A process uses pressure changes and a pressure compensation factor to estimate the rate at which neutral atoms are implanted. While implanting a first wafer using a first pressure compensation factor, the rate at which ions are implanted is determined. The first wafer is moved radially with respect to an ion beam while implanting ions into the first wafer so as to achieve a uniform total dose based on the rate at which ions are implanted and the estimated rate at which neutral atoms are implanted. The pressure is determined while implanting the first wafer, determining the pressure. A second pressure compensation factor is selected, that would have achieved a uniform rate of implanted ions plus implanted neutral atoms across a surface of the first wafer. The second pressure compensation factor is different from the first pressure compensation factor. The second pressure compensation factor is used to implant a second wafer. The second wafer is tested by forming a sheet resistance contour map.

Abstract: An apparatus and method thereof includes at least one acoustic transducer for receiving acoustic emissions produced during a semiconductor fabrication process. The acoustic transducer is mounted to various mechanical components of a semiconductor processing equipment in a manner so that the acoustic transducer receives acoustic emissions produced during the fabrication process. The received acoustic emissions are analyzed in in-situ to identify and determine surface characteristics of the wafer.

Abstract: A method of fabricating a trench capacitor of a memory cell, includes providing a semiconductor substrate with a surface covered by a pad layer, forming a trench in the substrate, forming a first layer on the pad layer and on the surface of the trench, removing a portion of the first layer to form a residual first insulating layer, forming a first conductive layer on the residual first layer, removing a portion of the first conductive layer, removing a portion of the residual first layer, driving out charged elements from the first layer into the semiconductor substrate, to form a first doped substrate region, removing the first layer, forming a node nitride on the trench, forming a second conductive layer on the pad layer and on the trench, removing a portion of the second conductive layer to form a second doped substrate region in the trench.

Abstract: A semiconductor device includes a trench formed in a substrate, and a diffusion region surrounding the trench to form a buried plate. A first conductive material is formed in the trench and connects to the buried plate through a bottom of the trench to form a first electrode. A second conductive material is disposed in the trench to form a second electrode. A node dielectric layer is formed between the first electrode and the second electrode.