Abstract: A processing sequence for definition of gate contacts can be implemented using either a deep ultra-violet (DUV) or mid ultra-violet (MUV) positive resist processing and supports the use of a reticle that integrates contacts to various regions including gates, sources and drains of various devices. In a one example, the wafer is coated with a planarizing anti-reflective coating (ARC), which then supports imaging of gate contacts using a positive DUV or MUV resist. This processing allows the nitride cap of certain transistor gates to be replaced with an oxide. In this example, the ARC can serve as an etch guide for selective removal of a film.

Abstract: A semiconductor device is provided having at least two neighboring transistors and an STI region therebetween. The STI region is provided with a voltage bias to minimize subthreshold leakage current between the neighboring transistors. A method of fabricating such a semiconductor device is also provided.

Abstract: A semiconductor memory device comprises a trench etched from a substrate below a shallow trench isolation and a doped collar oxide. The device further comprises a buried-strap junction formed adjacent to the shallow trench isolation and above the collar oxide, and a channel stop formed below the buried-strap junction, wherein a junction between the channel stop and the buried-strap junction is formed in the substrate.

Abstract: A system and method for determining the accuracy of the states of fuses by changing, or not changing, the state of additional fuses. The system includes a memory including addressable storage elements, address fuses whereby each fuse includes a link in a connected or disconnected state and the collective state of the address fuses identifies an address value, a parity fuse whereby the fuse includes a link in a connected or disconnected state and the state of the parity fuse represents a parity value, the parity value being based on, but not equivalent to, the address of an addressable storage element, and; an output providing a value dependant upon the address value and the parity value.

Abstract: A current measurement circuit and method for testing a semiconductor device is provided. The method includes the steps of providing a semiconductor integrated circuit device including a voltage regulating circuit, the voltage regulating circuit being activated as needed to maintain a required voltage level; monitoring the voltage regulating circuit to determine a number of times it is activated during a sample period; and comparing the number of activations to a predetermined limit whereby if the number of activations exceeds the predetermined limit the semiconductor device is defective. The current measurement circuit includes an external clock for providing a clock signal; a first counter for counting when the voltage regulating circuit is activated; a second counter for counting clock cycles of a sample period; and a register for storing the number of activations, wherein the number of activations represents a relative current consumption value of the semiconductor device.

Abstract: A fuse configuration for a semiconductor storage device is provided. The fuse configuration includes a first electrode formed in a dielectric layer, the first electrode having a first cross-sectional area defined by a first perimeter; a fuse element, or isolating layer, for coupling the first electrode to a second electrode; and the second electrode having a second cross-sectional area defined by a second perimeter, the first perimeter of the first electrode being larger than the second perimeter. By employing this modified capacitor layout, the fuse element, or isolating layer, will never come into contact with an edge of the first electrode, and thus eliminate a high electric field region from the fuse layout and reliability issues of the prior art fuse configurations. A method for forming the fuse configuration is also provided.

Abstract: A method for providing a compressed bit fail map, in accordance with the invention includes the steps of testing a semiconductor device to determine failed devices and transferring failure information to display a compressed bit map by designating areas of the bit map for corresponding failure locations on the semiconductor device. Failure classification is provided by designating shapes and dimensions of fail areas in the designated areas of the bit map such that the fail area shapes and dimensions indicate a fail type.

Abstract: A memory includes a memory array having a plurality of storage elements; a plurality of replacement storage elements; a plurality of address storage units, each operable to store a replacement address associated with a respective one of the replacement storage elements; a plurality of enable storage units, each operable to store at least first and second enable bits associated with a respective one of the replacement storage elements; and a decode unit operable to (i) activate one of the replacement storage elements when the at least first and second enable bits associated therewith are in an enable state and an input address matches the replacement address associated with the replacement storage element, and (ii) deactivate the replacement storage element when the at least first and second enable bits associated therewith have changed to a disable state.

Abstract: An improved process for cleaning a semiconductor wafer surface during manufacture to remove metallic contaminants without the use of robotics and without risk of scanning droplets falling from the wafer, in a faster time than with a manual process using a vacuum wand, comprising: a) positioning a wafer on a rotating plate pivotably mounted above a platform; b) contacting the wafer with a metals scanning solution droplet from the tip of a drop probe, the solution being adhered in a bottom portion of the drop probe above the wafer in a material of a surface tension sufficiently higher than the surface tension on the wafer, the drop probe being pivotably connected to a pivot arm which upon pivoting or turning one notch enables droplet sweeping of metal contaminants on a concentric circle on the wafer on the rotating plate; c) successively turning the pivot arm a sufficient number of notches to enable completion of wafer droplet sweepings through concentric circles to reach the edge of the wafer until all of t

Abstract: A semiconductor body-having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells.

Abstract: Disclosed is a method of testing memory, comprising providing one or more semiconductor wafers having one or more semiconductor chips thereon, each said chip comprising one or more memory cells, providing a programmable testing apparatus comprising at least one test pattern generators and a test bed adapted to receive said one or more wafers in communicative contact so as to address individual memory cells, chips, and wafers and transmit information thereto and receive information therefrom, receiving one or more test commands, constructing a test sequence of one or more commanded tests from said test commands, constructing at least one header comprising location information for each said wafer, chip and memory cell, testing said memory cells with a test pattern generated by said test pattern generator, collecting the results of said testing and passing them to a display device, passing said location information to said display device, constructing and displaying a graphical representation of said test result

Abstract: A method for displaying failure information for semiconductor devices, in accordance with the present invention, includes testing a semiconductor device with a tester to determine failures, and performing a redundancy calculation to repair the failures. The results of the redundancy calculation are stored in a file which identifies only addresses of components which have failed. The file is converted to a display format and the display format is displayed to provide a bit fail map for the semiconductor device such that sparse failures are displayed in addition to row and column failures without employing the tester to regenerate fail data.

Abstract: In accordance with the present invention, a method, which may be implemented by employing a program storage device, for determining yield loss for a device includes the steps of determining killing probabilities corresponding to values of inspection parameters based on historic inspection information, determining defects on the device and ordering the defects by classifying the defects according to the inspection parameters. The defects adopt the killing probabilities associated with the same values of the inspection parameters. The method further includes the step of calculating a predicted yield loss based on the defects and the adopted killing probabilities. The method further includes the step of applying statistical process control to the predicted yield loss for all in-line inspection (process) steps.

Abstract: A memory includes a memory array having a plurality of storage elements; a plurality of replacement storage elements; a plurality of address storage units, each operable to store a replacement address associated with a respective one of the replacement storage elements; a plurality of enable storage units, each operable to store at least first and second enable bits associated with a respective one of the replacement storage elements; and a decode unit operable to (i) activate one of the replacement storage elements when the at least first and second enable bits associated therewith are in an enable state and an input address matches the replacement address associated with the replacement storage element, and (ii) deactivate the replacement storage element when the at least first and second enable bits associated therewith have changed to a disable state.

Abstract: In a process of preparing a via in a semiconductor substrate wafer in which vias are landed on tungsten, and in which resist is stripped using plasma or chemical based processes that do not remove the veils formed during the etch, the improvement of concurrently removing veil material, controlling the interface of the tungsten, and stripping the resist, comprising: a) depositing and patterning tungsten on a substrate; b) depositing an oxide as an interlevel dielectric on the tungsten; c) patterning the oxide using photolithography and a photoresist; d) etching the oxide using a plasma generated etching method in which veils made up of metals, carbon based materials and oxide based materials are formed on the tungsten and sidewalls of the vias; and e) stripping the resist using a dry polymer removal method employing process gases and reducing gases to concurrently cause resist stripping, removal of the veils, and control of the tungsten interface.

Abstract: A method according to the present invention is provided for determining memory device identification. The method invokes a serial output from n identification fuses of two or more memory devices, the output for identifying the device, and sampling the serial output every nth bit to determine a fuse state for a fuse of each device. The method further repeats the sampling for all n fuses to acquire fuse data for all devices, and determines a pass/fail string corresponding to the sampled output, the pass/fail string being employed to identify the devices through a parallel test and burn-in system. The output is on an enabled data line which is used during the burn-in test wherein other data lines are disabled for avoiding bus contention. The method also includes storing the pass/fail string for the data in a database, and translating the pass/fail string using a structured query language expression executed against the database.

Abstract: A method for planarizing a dielectric layer on a semiconductor wafer while eliminating a mask and etch step, in accordance with the present invention includes providing a semiconductor wafer having trenches formed in a trench region of a substrate, and forming a dielectric layer on the semiconductor wafer to fill the trenches whereby up features form on flat surfaces of the wafer. An edge portion of the semiconductor wafer is polished to remove a portion of the dielectric layer about the edge portions of the semiconductor wafer. The dielectric layer is polished across the entire semiconductor wafer by employing a single non-stacked polishing pad and a slurry to planarize the trench regions and the up features in a single polish step such that a mask step and etch step for reducing the up features are eliminated from the polishing process.

Abstract: A system and method for improved throughput of semiconductor wafer processing. In one aspect, a wafer carrier is provided having a flat zone capable of holding an additional lot of wafers for processing. In addition, a multiple fork wafer transfer mechanism is provided having a plurality of wafer forks for loading and unloading wafers in the wafer carrier at a reduced fork pitch.

Abstract: A semiconductor body having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells.

Abstract: A method for providing specific test programs from a production test program for testing semiconductor devices, in accordance with the present invention, includes providing a semiconductor device to be tested by a tester and initiating a production test program. The production test program includes a plurality of program files and test code sequences. The production test program is held at a test which is to be extracted, and register information and settings are extracted from the tester for the test to be extracted. The register information and settings are stored in a storage file, and the storage file is assembled and translated to provide an executable test program for an extracted test for testing the semiconductor device or other semiconductor devices.