Abstract: Systems and methods for controlling access by a set of agents to a resource, where the agents have corresponding priorities associated with them, and where a monitor associated with the resource controls accesses by the agents to the resource based on the priorities. One embodiment is implemented in a computer system having multiple processors that are connected to a processor bus. The processor bus includes a shaping monitor configured to control access by the processors to the bus. The shaping monitor attempts to distribute the accesses from each of the processors throughout a base period according to priorities assigned to the processors. The shaping monitor allocates slots to the processors in accordance with their relative priorities. Priorities are initially assigned according to the respective bandwidth needs of the processors, but may be modified based upon comparisons of actual to expected accesses to the bus.

Abstract: A storage system or subsystem, method of locating components in the storage system and program product therefor. Storage system components have fiducial marks identifying component location. A sensor is located at an expected fiducial location and a first pass search for the fiducial is conducted along a search path. A second pass search, if needed, begins at a position located, horizontally, between the first pass start position and the system accessor home location.

Abstract: An evaluator system accepts input textual messages in unknown languages and assesses which character sets, corresponding to languages, matches that message. Textual messages whose individual characters are encoded in 16 bit Unicode or other universal format are parsed, and character sets which can express each character and the accumulated correspondence is logged. When the character sets against which the message is being tested only provide partial matches, the invention can determine which offers the best fit, including by means of a weighting function. The evaluation technology of the invention can be applied to multipart documents, and to search engines and indices.

Abstract: Methods are provided for overwriting data in a probe-based data storage device (1) wherein data is represented by the presence and absence of pits formed in a storage surface (4) by a probe of the device. Input data is first coded such that successive bits of a first value in the coded input data are separated by at least one bit of the other value. Overwrite data bits v0, v1, v2, . . . , are generated from the coded input data bits b0, b1, b2, . . . , and the overwrite data bits v0, v1, v2, . . . , are then used to overwrite data on the storage surface (4). According to a first method, the overwrite data bits are generated such that, if a pit represents a bit of said first value in the data storage device (1) then vi={overscore (b)}i?1, for i?1 and v0 has said first value, and if a pit represents a bit of said other value in the data storage device (1) then vi=bi?1 for i?1 and v0 has said other value.

Abstract: An optically connectable circuit board and optical components mounted thereon. At least one component includes optical transceivers and provides an optical connection to the board. Electronic components may be directly connected to the board electrically or optically. Also, some electronic components may be indirectly connected optically to the board through intermediate optical components.

Abstract: A CMOS static random access memory (SRAM) array with dynamically asymmetric cells, an integrated circuit (IC) chip including the SRAM and a method of accessing data in the SRAM. Each column of cells is connected to a pair of column supply lines supplying power to the column. During each SRAM access, a higher voltage is applied to one column supply line in each pair of the columns being accessed to unbalance cells in the columns being accessed. Unbalanced cells become asymmetric during accesses and the supply imbalance favors the data state being written/read.

Abstract: A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETS. Each FET includes a device gate along one side of a semiconductor (e.g., silicon) fin and a back bias gate along an opposite of the fin. Back bias gate dielectric differs from the device gate dielectric either in its material and/or thickness. Device thresholds can be adjusted by adjusting back bias gate voltage.

Abstract: A computer aided design (CAD) system. A template generation engine generates templates from interconnect configuration files. A field solver generates high frequency passive element relationships from the templates. A circuit builder generates circuit description files from device technology models and from high frequency passive element relationships. Parameterized circuit description models may be generated for large range of sensitivity analyses. A simulator simulates circuit responses for transmission line models from the circuit description files. Interconnect configuration files may be generated by a geometry and material definition module that receives process description data from a designer.

Abstract: Embedded devices typically have an operating system, one or more file-systems, as well as a bootloader and other data components resident in flash memory. During software development and testing, there is frequently a need to selectively update a combination of such images. The described technique organizes the images in the flash memory such that one can speed up the update process by eliminating relocation of existing images. A command-driven update mechanism provides a flexible process—eg, one can upload the images back to a host, one can update the update code itself, etc. A start handshake is used that enables auto-detection of the embedded serial port that is used for the update.

Abstract: A method and program product for optimizing level converter placement in a multi supply integrated circuit. Each level converter is placed at a minimum power point to minimize net power and transitional delay from a first (low) voltage net source through the level converter and to a second (higher) voltage net sink. Then, inefficient level converters are eliminated. Level converters with fanin cones below a selected minimum cone size are deleted and low voltage sources to the deleted level converter reverted. Higher voltage level circuit elements receiving inputs from multiple level converters are replaced with equivalent low voltage circuit elements. Low voltage buffer driving level converters are both replaced by a single said level converter.

Abstract: An integrated circuit (IC) including at least one combinational logic path. The combinational logic path includes two types of logic blocks cells that compensate each other for fabrication parameter effects on cell transistors. The two types may be dense cells with field effect transistor (FET) gates on contacted pitch and isolated cells with FET gates on wider than contacted pitch. Dense cell delay changes from the FET gates being printed out of focus are offset by isolated cell delay changes.

Abstract: Disclosed are a method, system and computer program product for placing a group order, mediated by a system having one or more computers, the method comprising the steps of: publishing, by a publisher, information about a quantity of a material; subscribing, via a subscriber, to a topic comprising said information; receiving, via a subscriber, said information; aggregating, via a subscriber, said information from at least one of said publishers; and responsive to said step of aggregating, selecting based on at least one criterion a best time to place said group order.

Abstract: A synchronous pipeline segment and an integrated circuit (IC) including the segment. The segment includes an input stage, an output stage and at least one intermediate stage. A place holder latch associated with each stage indicates whether valid stage data is in the stage. A local clock buffer provides a local clock gating a corresponding stage. The input and output stages are normally opaque and intermediate stages are normally transparent. Data items pass locally asynchronously between the input and output stages and are separated by opaque gated intermediate stages.

Abstract: A system and method for providing a printing capability using peripheral or stand-alone devices are disclosed. In the system and method, portions of a multimedia presentation, transcribed text, or both are output to a printing device. In the preferred embodiment, transcribed text is output to a fax machine by means of a Real Time Transcription Fax Server, which can also interleave other material into the fax output, and/or synchronize the fax output with other devices, such as monitors and speakers.

Abstract: A technique, system, and computer program for quickly and efficiently navigating through a comparison of different versions of a file. An abstract representation of the detected differences is provided in a separate navigation window or pane. This abstract representation is shown as one or more bars, which are formatted using one color for segments that are the same and a different color for those segments that are different. This allows the user to see, at a high level, the relative size of differences, the relative position of the differences, and how the differences are distributed throughout the files. The user can navigate through the differences using navigation controls that are synchronized between the navigation window (or pane) and a file comparison window. A novel use of hover help is defined. The navigation window and controls can be used with comparisons of any type of ordered data, such as text, audio, video, etc., and with comparisons of any number of versions of a file.

Abstract: The present invention provides an improved method, system, and computer program product that can optimize cache utilization. In one embodiment, a kernel service creates a storage map, and sending said storage map to an application. In one embodiment of the present invention, the step of the kernel service creating the storage map may further comprise the kernel service creating a cache map. In one embodiment of the present invention, the step of the kernel service creating the storage map may further comprise the kernel service creating an indication of one or more storage locations that have been allocated to store information for the application. In one embodiment of the present invention, the step of the kernel service creating the storage map may further comprise the kernel service creating the storage map in response to receiving a request for the storage map from the application.

Abstract: A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design, wherein the first digital design and the second digital design are intended to have a same logical function. A plurality of testcase types are then created by constraining one or more internal signals, and one or more test scripts representing the plurality of testcase types are produced. The method also includes verifying the second digital design with a testing simulation program by comparing results of the test scripts from the operational model and the reference model.

Abstract: An apparatus, system and method for cooling vertically stacked printed circuit boards (PCBs). In one embodiment, a first PCB is disposed within a substantially enclosed lower chamber inside a PCB containment housing. A second PCB is disposed above the first PCB within the housing to define a substantially enclosed upper chamber above the lower chamber. The second PCB includes one or more airflow apertures defined therethrough and providing vertical air flow coupling between the upper and lower chambers. An airflow actuating device is utilized to generate a primary forced airflow within the upper chamber which is substantially parallel to the surface plane of the second PCB. The primary forced airflow further induces a negative air pressure in the upper chamber such that a mixed convection airflow is established between the upper and lower chambers via the second PCB apertures.

Abstract: A low dielectric constant, patterned, nanoporous material and a method of forming the material. The material is formed by depositing a layer onto a substrate, said layer comprising a reactive organosilicate material, a porogen, an initiator, and a solvent; exposing portions of the layer to energy (e.g., thermal energy or electromagnetic radiation) to change the solubility of portions of the organosilicate material with respect to the solvent; selectively removing more soluble portions of the layer to generate a relief pattern; and decomposing the porogen to thereby generate a nanoporous organosilicate layer.

Abstract: An integrated circuit system having a plurality of macros is provided. The integrated circuit system includes an external voltage supply input configured for supplying an external voltage to the integrated circuit; and a plurality of internal voltage supply generators, each of the plurality of internal voltage supply generators being connected to a respective macro of the plurality of macros and configured for receiving the external voltage via the external voltage supply input for generating an internal voltage supply for operating its respective macro. Each of the plurality of internal voltage supply generators includes circuitry for generating the internal voltage supply and circuitry for disconnecting at least a portion of its respective macro. The integrated circuit system can be applied to a semiconductor chip to save active or stand-by power. It can also be used to disconnect a defective portion of the chip and optionally replace it with a non-defective portion of the chip.