Dual gate FinFet
A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETS. Each FET includes a device gate along one side of a semiconductor (e.g., silicon) fin and a back bias gate along an opposite of the fin. Back bias gate dielectric differs from the device gate dielectric either in its material and/or thickness. Device thresholds can be adjusted by adjusting back bias gate voltage.
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1. Field of the Invention
The present invention is related to semiconductor devices and manufacturing and more particularly to field effect transistors (FETs) formed on silicon on insulator (SOI) wafers and methods of manufacturing FETs and circuits on SOI wafers.
2. Background Description
Semiconductor technology and chip manufacturing advances have resulted in a steady increase of on-chip clock frequencies, the number of transistors on a single chip and the die size itself, coupled with a corresponding decrease in chip supply voltage and chip feature size. Generally, all other factors being constant, the power consumed by a given clocked unit increases linearly with the frequency of switching within it. Thus, not withstanding the decrease of chip supply voltage, chip power consumption has increased as well. Both at the chip and system levels, cooling and packaging costs have escalated as a natural result of this increase in chip power. For low end systems (e.g., handhelds, portable and mobile systems), where battery life is crucial, net power consumption reduction is important but, must be achieved without degrading performance below acceptable levels.
To minimize power consumption, most integrated circuits (ICs) used in such low end systems (and elsewhere) are made in the well-known complementary insulated gate field effect transistor (FET) technology known as CMOS. A typical CMOS circuit includes paired complementary devices, i.e., an n-type FET (NFET) paired with a corresponding p-type FET (PFET), usually gated by the same signal. Since the pair of devices have operating characteristics that are, essentially, opposite each other, when one device (e.g., the NFET) is on and conducting (ideally modeled as a closed switch), the other device (the PFET) is off, not conducting (ideally modeled as an open switch) and, vice versa.
For example, a CMOS inverter is a series connected PFET and NFET pair that are connected between a power supply voltage (Vdd) and ground (GND). Both are gated by the same input and both drive the same output, the PFET pulling the output high and the NFET pulling the output low at opposite input signal states. Ideally, when the gate of a NFET is below some positive threshold voltage (VT) with respect to its source, the NFET is off, i.e., the switch is open. Above VT, the NFET is on conducting current (Ion), i.e., the switch is closed. Similarly, a PFET is off (Ioff=0) when its gate is above its VT, i.e., less negative, and on below VT. Thus, ideally, the CMOS inverter in particular and CMOS circuits in general pass no static (DC) current. So, ideally, device on to off current ratios (Ion/Ioff) are very large and, ideal CMOS circuits use no static or DC power, consuming only transient power from charging and discharging capacitive loads.
In practice however, transient power for circuit loads accounts for only a portion of the power consumed by CMOS circuits. A typical FET is much more complex than a switch. FET drain to source current (and so, power consumed) is dependent upon circuit conditions and device voltages. FETs are known to conduct what is known as subthreshold current below threshold for NFETs and above for PFETs. Subthreshold current increases with the magnitude of the device's drain to source voltage (Vds) and inversely with the magnitude of the device VT. Among other things, VT is inversely proportional to gate oxide thickness and, to some extent channel length, both of which are related to feature size. In addition, gate leakage, to channel, to source or drain and gate induced drain leakage (GIDL) can also contribute to static power and are also related in particular to oxide thickness. Thus, as chip features shrink, these leakage sources become more predominant. This is especially true in what is known as partially depleted (PD) silicon on insulator (SOI) technology, where subthreshold leakage has been shown to increase dramatically, such that it may be the dominant source of leakage. When multiplied by the millions and even billions of devices on a state of the art IC, even 100 picoAmps (100 pA) of leakage in each devices, for example results in chip leakage on the order of 100 milliAmps (100 mA). So, increasing device thresholds reduces subthreshold leakage and other short channel effects. Unfortunately, however, increasing device thresholds also impairs performance. Fin shaped FETs (FinFETs) are known to have better short channel effect control than partially depleted SOI FETs and it is easier to manufacture dual gate FinFETs than planar fully depleted double gate FETs. However, FinFET channels are too thin and too short for consistent channel tailoring (i.e., fin doping fluctuates unacceptably) and so, consistent FinFET thresholds have not heretofore been attainable.
Thus, there is a need for improved VT adjustment to achieve better leakage control, steeper subthreshold slopes and increased device on to off current ratios.
SUMMARY OF THE INVENTIONIt is a purpose of the invention to improve device on to off current ratios;
It is another purpose of the invention to improve device subthreshold slopes;
It is yet another purpose of the invention to improve device leakage control.
The present invention relates to a field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETS. Each FET includes a device gate along one side of a semiconductor (e.g., silicon) fin and a back bias gate along an opposite of the fin. Back bias gate dielectric differs from the device gate dielectric either in its material and/or thickness. Device thresholds can be adjusted by adjusting back bias gate voltage.
The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:
Turning now to the drawings and, more particularly,
Next, as shown in
Continuing step 106 in
Next, in
Next, in step 108 as shown in
Device gate formation begins in step 110 as shown in
As shown in
Step 104 of defining device fins begins in
Next, fin formation begins in step 106 as shown in
Back bias gate formation in step 108 begins in
The device gate layer is formed step 112, beginning in
It should be noted that the above described device materials are for example only and not intended as a limitation. In particular, the gate material (and correspondingly back bias gate material) may be may be polysilicon, a silicide, a metal or any suitable conductive material. Further, in one preferred embodiment device, the gate dielectric is an oxide and the back bias gate dielectric is a high K dielectric. Since most of the device current flow occurs at the device gate, gate oxide can provide a good interface for current flow, whereas a high K gate dielectric may impair mobility. Mobility is not an issue for the back bias gate and so, since the back bias gate is used for control purpose only, the back bias gate dielectric may be a high K dielectric.
Advantageously, dual gate FinFET formed according to the present invention have different thicknesses and may have different gate dielectrics because gate dielectrics for the device gate is formed separately and independently of back bias gate dielectrics. Further, back bias gates may be used for independently adjusting device threshold by applying a bias voltage that may be constant or time varying, depending upon device type, i.e., n-type FinFET or p-type FinFET. Further, time varying voltage can be used to allow dynamic threshold variation for preferred embodiment FinFETs. Thresholds can be increased for significantly reduced device leakage and reduced for performance, especially in large chip subunits; e.g., raising thresholds during dormant periods for reduced leakage (and reduced power consumption) and lowering threshold for higher drive current and better performance during active periods.
While the invention has been described in terms of preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.
Claims
1. A field effect transistor (FET) comprising:
- a fin formed on a dielectric surface;
- a device gate along one side of said fin;
- a back bias gate along all opposite side of said fin;
- a device gate dielectric along one first side between said device gate and said fin; and
- a back bias gate dielectric along said opposite side between said back bias gate and said fin, wherein said back bias gate dielectric differs from said device gate dielectric in material, wherein one of said device gate dielectric and said back bias gate dielectric is a layered dielectric comprising at least 2 dielectric material layers.
2. A FET as in claim 1, wherein said back bias gate dielectric is thicker than said device gate dielectric.
3. A FET as in claim 1, wherein each of said back bias gate dielectric and said device gate dielectric is selected from a group of materials consisting of an oxide, an oxynitride and a high K dielectric.
4. A FET as in claim 1, wherein said device gate and said back bias gate are a conductive material selected from a group of materials consisting of a metal, doped silicon, doped germanium, doped silicon germanium and a metal silicide.
5. A FET as in claim 1, wherein said fin is a semiconductor fin selected from a group of materials consisting of silicon, germanium and silicon-germanium.
6. A FET as in claim 5, wherein said fin is a silicon fin.
7. A FET as in claim 6, wherein said dielectric surface is an oxide layer.
8. A WET as in claim 7, wherein said oxide layer is a buried oxide layer.
9. A FET as in claim 7, wherein said oxide layer is disposed on a nitride layer.
10. A FET as in claim 6, further comprising a dielectric pillar above said silicon fin.
11. A FET as in claim 10, wherein said dielectric pillar is a nitride pillar.
12. A FET as in claim 11, wherein said nitride pillar forms a cap between said device gate and said back bias gate.
13. An integrated circuit (IC) on a semiconductor on insulator (SOI) chip, said IC including a plurality of field effect transistors (FETs) disposed on an insulating layer, each of said FETs comprising:
- a semiconductor fin formed on an insulating layer;
- a device gate dielectric along a first side of said semiconductor fin;
- a device gate along said device gate dielectric;
- a back bias gate dielectric along an opposite side of said semiconductor fin; and
- a back bias gate along said back bias gate dielectric, wherein said back bias gate dielectric is five times (5×) thicker than said device gate dielectric.
14. An IC as in claim 13, wherein each of said back bias gate dielectric and said device gate dielectric is selected from a group of materials consisting of an oxide, an oxynitride and a high K dielectric.
15. An IC as in claim 13, wherein said gate and said back bias gate are a conductive material selected from a group of materials consisting of a metal, doped silicon, doped germanium, doped silicon germanium and a metal silicide.
16. An IC as in claim 13, wherein said dielectric surface is an oxide layer.
17. An IC as in claim 16, wherein said oxide layer is a buried oxide layer.
18. An IC as in claim 16, wherein said oxide layer is disposed on a nitride layer.
19. An IC as in claim 13, each said FET further comprising a dielectric pillar above said semiconductor fin.
20. An IC as in claim 19, wherein said semiconductor is silicon.
21. An IC as in claim 19, wherein said dielectric pillar is a nitride pillar.
22. An IC as in claim 21, wherein said nitride pillar forms a cap between said device gate and said back bias gate.
23. An integrated circuit (IC) on a semiconductor on insulator (SOI) chip, said IC including a plurality of field effect transistors (FETs) disposed on an insulating layer, each of said FETS comprising:
- a semiconductor fm formed on an insulating layer;
- device gate dielectric along a first side of said semiconductor fin;
- a device gate along said device gale dielectric;
- back bias gate dielectric along an opposite side of said semiconductor fin;
- a back bias gate along said back bias gate dielectric, wherein said back bias gate dielectric differs from said device gate dielectric in material, wherein one of said device gate dielectric and said back bias gate dielectric is a layered dielectric comprising at least 2 dielectric material layers.
24. An IC as in claim 23, wherein said device gate and said back bias gate are a conductive material selected from a group of materials consisting of a metal, doped silicon, doped germanium, doped silicon germanium and a metal suicide.
25. An IC as in claim 23, wherein said dielectric surface is an oxide layer.
26. An IC as in claim 25, wherein said oxide layer is a buried oxide layer.
27. An IC as in claim 25, wherein said oxide layer is disposed on a nitride layer.
28. An IC as in claim 23, each said FET further comprising a dielectric pillar above said semiconductor fin.
29. An IC as in claim 28, wherein said semiconductor is silicon.
30. An IC as in claim 28, wherein said dielectric pillar is a nitride pillar.
31. An IC as in claim 30, wherein said nitride pillar forms a cap between said device gate and said back bias gate.
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Type: Grant
Filed: Nov 20, 2003
Date of Patent: Aug 15, 2006
Patent Publication Number: 20050110085
Assignee: International Business Machines Corp. (Armonk, NY)
Inventors: Huilong Zhu (Poughkeepsie, NY), Jochen Beintner (Wappingers Falls, NY), Bruce B. Doris (Brewster, NY), Ying Zhang (Yorktown Heights, NY)
Primary Examiner: Ida M. Soward
Attorney: Law Office of Charles W. Peterson, Jr.
Application Number: 10/717,737
International Classification: H01L 29/76 (20060101); H01L 29/94 (20060101); H01L 31/062 (20060101); H01L 31/113 (20060101); H01L 31/119 (20060101);