Abstract: An apparatus for depositing an electrically conductive layer on the surface of a wafer comprises a flange. The flange has a cylindrical wall and an annulus attached to a first end of the cylindrical wall. The annulus shields the edge region of the wafer surface during electroplating reducing the thickness of the deposited electrically conductive layer on the edge region. Further, the cylindrical wall of the flange can be provided with a plurality of apertures adjacent the wafer allowing gas bubbles entrapped on the wafer surface to readily escape.

Abstract: An interface for expanding the number of SCSI hosts that can access a storage array includes a SCSI interface chip for receiving a SCSI command from a host via a SCSI bus, a domain indicator for providing a domain number assigned to the SCSI chip, a memory device for storing data and code, and a processing unit responsive to the code and operative to generate a device address from the domain number, the target number, and the logical unit number, and to execute the SCSI command with a particular device of the storage array corresponding to the device address. The domain indicator may be either hardware based (e.g., a mechanical selector switch) or software based (e.g. written to a data storage device of the interface via a SCSI host or WIE the storage array).

Abstract: A structure for packaging an electronic device.

Abstract: A computing system that incorporates the invention includes a host processor which is coupled to a memory subsystem via a first bus system, a controller device and a second bus system. The controller device includes memory for storing plural Scripts for replay to the host processor, for instance, via the second bus system. A Script is an instruction set used to execute operations on a controller device. Each Script includes one or more addresses where either message or status data (or other operational data) can be found which is to be inserted, prior to dispatch of the Script. During operation of the computing system, the memory subsystem is caused, as a result of its operation, to issue an instruction to the controller device to dispatch a Script to, for instance, the host processor. The controller device responds by accessing the required Script, playing the Script which results in accesses to locally stored operational data for inclusion into the Script.

Abstract: An improved field effect transistor (FET) structure is disclosed. It comprises a first insulator layer containing at least one primary level stud extending through the layer; an undoped cap oxide layer disposed over the insulator layer and abutting the upper region of each stud; a primary level thin film transistor (TFT) disposed over the undoped cap oxide layer; and a planarized oxide layer disposed over the TFT. Multiple TFT's can be stacked vertically, and connected to other levels of studs and metal interconnection layers. Another embodiment of the invention includes the use of a protective interfacial cap over the surface of tungsten-type studs. The FET structure can serve as a component of a static random access memory (SRAM) cell. Related processes are also disclosed.

Abstract: A printing system wherein a first print driver utilizes an Intelligent Printer Data Stream (IPDS) to send a first job at a first font resolution to a printer and a second job at a second font resolution or a second job utilizing a non-IPDS data stream to the printer. A second print driver also utilizing the IPDS data stream is connected to the same printer for sending a third job. By sending a "Manage IPDS Dialog (MID)" IPDS command to the printer upon conclusion of the first job, the printer is enabled to switch immediately to the second job. The printer is enabled to switch between the first and second print drivers by use of the MID command at the conclusion of a print job.

Abstract: Thin-film conductor technology is utilized to form resistors of precisely controlled value within the interior of multi-chip modules to properly terminate network circuits which interconnect one or more chips with either output pin connections or other chips on the multi-chip module. By forming and disposing the resistors within the interior of the multi-chip module, the terminating resistors may be manufactured during the multi-chip module manufacturing process. This approach preserves valuable surface area available for interconnecting the computer chips to the multi-chip module rather than consuming scarce surface area with termination resistors and other circuit elements necessary to adapt the multi-chip module and the other computer chips to each other.

Abstract: A single reliable clock source that can be shared by all cards in a multiple card assembly. The clock delivers synchronous clock signals, so that there is no longer a need to provide crystal oscillators on each card, instead, a single non-interruptable clock source is shared by all cards. The clock is an Application Specific Integrated Circuit (ASIC), where single sources of failure have been removed by using redundant connection and majority logic. Thus, a plurality of selection means are redundantly coupled to receivers for selecting an oscillator signal to provide to phase-locked oscillators. Further, majority logic voters are redundantly coupled to the phase-locked oscillator to provide a clock output signal reflecting the state of the majority of the phase-locked oscillator signals. The clock includes three independent crystal oscillators, one clock ASIC, the wire and connectors which deliver the signals, and a 2.times.3 AND-OR majority logic on the receiving card.

Abstract: A computer system, and its parallel and serial implementations, its serial and parallel network and multi-processor configurations, with tight and loose coupling among processors. The computer system has a CAM coupled to the computer system or imbedded therein. CAM requests may be processed serially, or as parallel queries and coupled with PAPS (Parallel Associative Processor System) capabilities (P-CAM). The computer system may be configured as an expert system preferably having combined tuple space (TS) and CAM (content addressable memory) resources, an inference engine and a knowledge base. As an expert system, improvements for production processing are provided which surpass prior art performance represented by RETE and CLIPS. An inferencing process for production systems is disclosed, and a process for working memory element assertions.

Abstract: Grooved substrates and multilayer structures, especially suitable for optical disks, are taught. The major process steps include spin coating of a supporting plate with dissolved material forming a soft layer thereon, stamping grooves into the soft layer to form a structured soft layer showing the negative image of the stamp and hardening the structured soft layer by thermal treatment. The dissolved material contains polymeric organometal compounds comprising polymer siloxane and/or polymer silicates. In one embodiment the structured soft layer is a dielectric layer containing various combinations of the oxides SiO.sub.2, La.sub.2 O.sub.3, PbO and TiO.sub.2. The multilayer structure completed by a magneto-optic layer, a reflector layer and a passivation layer.

Abstract: Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication.

Abstract: Surface modification of magnetic recording heads using plasma immersion ion implantation and deposition is disclosed. This method may be carried out using a vacuum arc deposition system with a metallic or carbon cathode. By operating a plasma gun in a long-pulse mode and biasing the substrate holder with short pulses of a high negative voltage, direct ion implantation, recoil implantation, and surface deposition are combined to modify the near-surface regions of the head or substrate in processing times which may be less than 5 min. The modified regions are atomically mixed into the substrate. This surface modification improves the surface smoothness and hardness and enhances the tribological characteristics under conditions of contact-start-stop and continuous sliding. These results are obtained while maintaining original tolerances.

Abstract: An architecture is disclosed for communication of remote devices to a digitizing display. The architecture includes a contact sensing erasure mechanism and a position sensing erasure mechanism whose outputs are multiplexed for transmission from the stylus to an antenna located proximate to the digitizing display. The digitizing display will erase text or graphics data in a pen-based computer system in response to the stylus. A calibration method provides improved accuracy for the erasure function.

Abstract: A program arrangement presently disclosed provides support within an operating system for a commonly used class of peripheral devices (e.g. mouse devices or, more generally, pointing devices). This arrangement effectively eliminates dependencies between device driver software associated with the supported device(s) and system (and/or application) software; so that device driver software can be created without extensive knowledge of the operating system and system software can be modified cost effectively without affecting the usefulness of existing device drivers. In this arrangement, device driving functions are assigned to two discretely separate program modules having a standardized interface. One module, included in the operating system, provides a device-independent base for coordinating device and system interaction. The other module is associated specifically and directly with supported devices, and can be created by programmers having little knowledge of the internal structure of the system software.

Abstract: A shift register comprises a plurality of amorphous silicon thin-film transistors configured in a plurality of register cells through which data is shifted through a plurality of amorphous silicon thin-film floating-gate transistors. In the event power is cutoff or lost, the floating gate transistors non-volatilely store the data which can be recovered or restored when power is subsequently turned on. Each cell comprises two stages in which data signals are written before being input into the next stage and next cell. A clock generator receives clocking signals for controlling the shifting of data through the register.

Abstract: A logic circuit mechanism for inducing a processing unit to release a LOCK signal that the processing unit uses to secure continuous access to a memory system during read modify write operations requiring "atomic" (continuous) access. The processing unit has an internal cache enabling it to set up consecutive memory access operations at a pace such that the LOCK signal could be held continuously active while a string of atomic memory accesses is carried out. The present circuit mechanism prevents premature release of the processing unit's LOCK signal, by asserting a Hold signal which requires the processing unit to release its LOCK signal but only after that unit has fully completed its current atomic access operation.

Abstract: Hybrid compression processes for digital color video data that enables software only playback of the compressed digital video in low-end computers, wherein intraframe and interframe compression techniques are brought together through a sequence of procedures that analyze local frame regions, integrate unique processes with block truncation coding compression, and adopt the advantages of visual pattern image coding for color video. The process determines the appropriate encoding of each local frame region with one of various compression techniques, based upon its image properties. The compression methods retain the fidelity of the original video data to provide high quality video during decompression and reconstruction of high motion and textured video clips, while simultaneously providing sufficient compression and ease of decoding for software-only decompression thereby exhibiting properties that enable good quality video to be displayed in low-end computers.

Abstract: Disclosed is a multi-compartment electroplating tank and a process for using the tank to simultaneously plate dissimilar materials onto a substrate.

Abstract: An AC-coupled receiver is provided which allows data with long periods of no signal sent on a fiber optic bus to be received without the normally required preamble. The receiver provides a voltage signal which is AC-coupled to one side of a differential amplifier with a delayed voltage signal AC-coupled to the other input of the differential amplifier. If the time constant of the AC coupling network is much longer than the signal baud time, low-frequency variations at the two inputs of the differential amplifier will be nearly identical and the low frequency signals will effectively cancel each other.

Abstract: The lead free alloy is a low solidus temperature, multi-component solder alloy containing at least about 50 weight percent Bi, up to about 50 weight percent Sn (basis total Sn and Bi), and an effective amount of a physical and mechanical property enhancing third component. The third component can be Cu, In, Ag, and combinations of Cu and Ag.