Abstract: Bias circuits to stabilize oscillation in ring oscillators, oscillators, and methods to stabilize oscillation in ring oscillators are provided. The ring oscillator includes a plurality of differential delay cells, each including a pair of input transistors, a pair of voltage-controlled resistors, and a common current source. The bias circuit includes a replica arm that includes a replica of one of the voltage-controlled resistors, and a resistor arm that includes a fixed resistor. The bias circuit supplies bias voltages to the differential delay cells such that ratio of voltage swing to bias current of the delay cell is kept constant by referring the ratio to the fixed resistor.

Abstract: A semiconductor device that prevents a build-up of electrostatic charge in a dummy pad is provided. The semiconductor device may contain an internal circuit formed on a semiconductor substrate and the dummy pad which is not electrically connected to the internal circuit. The semiconductor device may further include a seal ring that surrounds the internal circuit and the dummy pad, where the seal ring is electrically connected to the semiconductor substrate and includes a pattern in a first metal layer, a contact between the pattern in the first metal layer and the semiconductor substrate, patterns in upper metal layers stacked above the pattern in the first metal layer, and multiple electrical contacts between the patterns in the first metal layer and the upper metal layers, in which the dummy pad is electrically connected to the seal ring.

Abstract: Various exemplary embodiments provide methods of controlling frame memory, memory control circuits, and image processing apparatuses including the memory control circuits. Data representing values of pixels constituting each of a plurality of frames are received in an order of the frames, and data representing values of pixels constituting a previous frame are read from the frame memory and data representing values of pixels constituting a next frame are written to the frame memory. By reading first data representing values of a portion of the pixels constituting the previous frame from the frame memory before receiving of data representing values of pixels constituting the next frame starts, a delay time before starting to output data representing values of pixels of the previous frame can be shortened.

Abstract: A semiconductor integrated circuit that includes a circuit element with a reduced parasitic capacitance and has a short start-up time. A well of the different type of conduction from that of the substrate is formed in the area of the surface of the semiconductor substrate under the circuit element. A constant voltage, which biases the junction between the well and the semiconductor substrate in a reverse direction, is applied to the well through a resistor having a higher impedance compared with the impedance of the capacitance of the reverse-biased junction between the well and the substrate at the frequency of the signal applied to the circuit element.

Abstract: In an output driver circuit, a replica circuit includes seventh and eighth transistors corresponding to first and second transistors, respectively, ninth and tenth transistors corresponding to third or fifth, and fourth or sixth transistors in a driver circuit, respectively, and a resistor corresponding to a termination resistor. A reference voltage and a voltage of a node between the ninth transistor and the resistor are input to an operational amplifier, and an output signal of the operational amplifier is input to gates of the first and seventh transistors.

Abstract: An access area is set within an address space of a dynamic random access memory by arranging two or more complete columns of blocks, in which blocks of memory cells are arranged within an entirety of a specified range of row addresses, along a direction of column addresses. Each of the blocks includes memory cells positioned at a same row address and a specified number of consecutive column addresses. The total number of blocks arranged in the access area is just capable of storing the number of words of the data to be stored. The two or more complete columns of blocks are successively accessed by successively accessing the blocks arranged in each of the columns of blocks. Thereby, a refresh operation of the dynamic random access memory is made unnecessary.

Abstract: A switching-type power-supply which enables the switching with little power loss and a method of switching the switching-type power-supply are provided. The switching-type power-supply unit includes a transformer with primary, secondary, winding and control windings, a switch which switches supply of a primary current from a dotted terminal to a non-dotted terminal through the primary winding, a rectifying diode connected the secondary winding, a monitoring signal generation circuit with a diode and a resistor, the diode between GND and a dotted terminal of the control winding, the resistor between GND and a non-dotted terminal of the control winding, the monitoring signal generation circuit generating a monitoring signal at the dotted terminal of the control winding, and a control unit with a zero-point detector and a controller. The zero-point detector monitoring the monitoring signal and supplying a detection signal to the controller.

Abstract: A data transfer apparatus includes at least one master and a plurality of slaves connected by a ring-connection bus, and a controller having a master port and slave ports connected to the corresponding master and slaves, respectively. In such a ring-like structure, a large amount of data can be transferred efficiently, and even if data continuously flows on the bus, data transfer is performed in a master/slave structure, thereby reducing the overall data transfer time.

Abstract: An exemplary semiconductor integrated circuit is formed on a surface of a semiconductor chip includes a circuit region and a dummy region on the surface of the semiconductor chip. The circuit region includes a plurality of circuit patterns, which form circuit elements of the semiconductor integrated circuit, in a plurality of pattern layers. The dummy region includes a plurality of character dummies, which do not contribute to an operation of the semiconductor integrated circuit. The character dummies have a fixed shape and dimension, and arranged in a character pattern layer selected from the plurality of pattern layers with a fixed pitch. The dummy region further includes an identification sign formed by connecting selected ones of the character dummies chosen from the plurality of the character dummies.

Abstract: A semiconductor integrated circuit has an active mode and a sleep mode. The semiconductor integrated circuit is constructed by alternately connecting a plurality of combinational logic circuits and a plurality of flip-flops. The flip-flops include a retention flip-flop that is supplied with electric power and retains the data in the sleep mode, and a non-retention flip-flop that is not supplied with electric power during the sleep mode. The non-retention flip-flop includes an initializing circuit that initializes the non-retention flip-flop when the semiconductor integrated circuit is switched from the sleep mode to the active mode.

Abstract: An exemplary cell library includes a first plurality of types of standard cells. Each of the first plurality of types of standard cells includes threshold voltage adjusting patterns. The upper and the lower boundaries of the threshold voltage adjusting patterns contact the upper and lower boundaries of the cell frame and the distances between the left and right boundaries of the threshold voltage adjusting patterns and the cell frame are set appropriately. Accordingly, it is possible to place standard cells including transistors with different threshold voltages at arbitrary positions without increasing the area of a circuit block or the design cost.

Abstract: Methods, apparatus and systems perform searches in a CAM memory that is divided into one or more databases. A selector selects at least two the databases for a simultaneous search, and selects at least one of the databases for a sequential search.

Abstract: Exemplary embodiments of color conversion circuits and color conversion methods convert input color data into output color data. The input color data is positioned in a three-dimensional color space, which is divided into a plurality of unit cubes each having a fixed dimension. The input color data is converted by performing interpolations using conversion coefficients at vertexes of the unit cube within which the input color data is positioned. When the input color data is positioned on a gray axis of the color space, a substitution circuit substitutes some of the conversion coefficients such that the interpolation becomes a linear interpolation. As a result, it is assured that input color data positioned on the gray axis is converted to gray output color data.

Abstract: A method of testing a semiconductor integrated circuit is disclosed. Specifically, a method of testing a semiconductor integrated circuit comprising a plurality of flip-flops is provided. The disclosed method includes connecting the plurality of flip-flops in series so that the plurality of flip-flops forms a scan-chain; inputting data to the scan-chain while supplying a clock signal to the plurality of flip-flops so that the data is set in the plurality of flip-flops; retaining the data in the plurality of flip-flops while inhibiting the clock signal for a predetermined period; restarting the clock signal to the plurality of flip-flops so that the data retained in the plurality of flip-flops is output from the scan-chain; and comparing the data output from the scan-chain and the data input to the scan-chain to test data retention of the plurality of flip-flops.

Abstract: A test circuit and a method of monitoring a manufacturing process of a semiconductor integrated circuit using the test circuit are provided. The test circuit comprises elements to be tested; a selection circuit for sequentially selecting at least one of the elements at a time. The test circuit and pads used for testing the elements are placed within a scribe line on a semiconductor wafer.

Abstract: An output driver circuit including a pre-driver stage that receives a first data signal, the pre-driver stage including a plurality of first differential pairs that perform current subtraction to output a second data signal based on the first data signal, and an output driver stage electrically coupled to the pre-driver stage that receives the second data signal from the pre-driver stage, the output driver stage including a plurality of second differential pairs that transmit an output signal along transmission lines.

Abstract: An output buffer circuit, which minimizes or prevents output delay of output signal and degradation of slew rate while suppressing overshoot and undershoot, is provided. In a first time period when an input signal to a gate of an N-channel output transistor changes from ‘L’ level to ‘H’ level, the gate is connected to an output terminal through a capacitor element so that the overshoot is suppressed. In addition, the output buffer circuit stores negligible electrical charge in the capacitor element prior to the first time period, which results in minimal delay in outputting a buffered signal and degradation of slew rate while suppressing undershoot when the input signal changes from ‘H’ level to ‘L’ level in the first time period.

Abstract: The main surface of a quartz component is divided by an offset into a first region having a larger height around an inner perimeter and a second region adjacent to the outer perimeter of the first region. Repeated restoration of a damaged component by forming a bulge on the first region and machining the bulge to make a flat surface while maintaining the offset enables long term use of the component.

Abstract: A method and an apparatus for driving passive matrix liquid crystal, comprising the steps of: simultaneously selecting Y row electrodes, where Y is an odd number of 7 and above; calculating an exclusive OR between a Y-bit row selection vector representing a selection pattern of the Y row electrodes and Y-bit ON/OFF display data representing a display pattern of column electrodes, for each corresponding bit; adding the exclusive ORs for each bit; when X=(Y+1)/2, and a 1/(X?1) voltage of the maximum voltage of the column electrodes is Vc, selecting a voltage level of the column electrodes from X voltage levels satisfying: [2×i?(X?1)]×Vc (i=an integer of 0 to (X?1)) in accordance with the result of the addition for driving. These method and apparatus prevent the frame response phenomenon of high-speed liquid crystal while realizing high-contrast display, low-voltage driving, low power consumption, and reduction in chip size.

Abstract: Standard cell libraries and methods of designing semiconductor integrated circuits are provided. At least one of delay-adjusting cell data and load-capacitor cell data is stored in the cell library for a specified type standard cell in addition to the standard cell data. The specified type standard cell may be utilized as a delay-adjusting cell or a load-capacitor cell. Accordingly, precise adjustment of delay times during designing a semiconductor integrated circuit is enabled without requiring registering a new standard cell in the cell library. Semiconductor integrated circuits are also provided that are configured to allow precise adjustment of delay times in the semiconductor integrated circuits.