Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

Abstract: A semiconductor memory device includes: a first wiring; a first memory transistor; a first transistor; a second memory transistor; a second transistor; a second wiring connected to a gate electrode of the first memory transistor; a third wiring; a first gate wiring connected to a gate electrode of the first transistor; a second gate wiring connected to a gate electrode of the second transistor; and a control circuit configured to execute an erase operation that selects the first or the second memory transistor. The control circuit controls a voltage of the first gate wiring to become larger than a voltage of the second wiring and controls a voltage of the second gate wiring to become larger than the voltage of the first gate wiring in the erase operation performed with the first memory transistor selected.

Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistance effect element including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a variable magnetization direction, a third magnetic layer having a fixed magnetization direction and a nonmagnetic layer, the first magnetic layer being provided between the second and third magnetic layers, and the nonmagnetic layer being provided between the first and third magnetic layers. The second magnetic layer has a superlattice structure in which first element layers and second element layers are alternately stacked. The first element is Co, and the second element is selected from Pt, Ni and Pd, and the second magnetic layer contains Cr as a third element.

Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.

Abstract: A semiconductor device includes a semiconductor layer including first and second regions and a third region therebetween, a gate insulating layer between the third region and a gate electrode, first and second electrodes connected to the first and second regions in a first direction, a first conductive layer between the first region and the first electrode and/or between the second region and the second electrode. The first conductive layer includes a metal element, aluminum, and nitrogen, and has first and second portions. An atomic concentration of the metal element is higher than that of aluminum in the first portion. An atomic concentration of aluminum is higher than that of the metal element in the second portion. The device further includes a second conductive layer between the oxide semiconductor layer and the first conductive layer. The second conductive layer includes oxygen and at least one of indium, zinc, tin, and cadmium.

Abstract: Provided is a semiconductor device of the embodiment including: an oxide semiconductor layer; a gate electrode; a first electrode electrically connected to one portion of the oxide semiconductor layer, the first electrode including a first region, second region, a third region, and a fourth region, the first region disposed between the first portion and the second region, the first region disposed between the third region and the fourth region, the first region containing at least one element of In, Zn, Sn or Cd, and oxygen, the second region containing at least one metal element of Ti, Ta, W, or Ru, the third region and the fourth region containing the at least one metal element and oxygen, the third region and the fourth region having an atomic concentration of oxygen higher than that of the second region; and a second electrode electrically connected to another portion of the oxide semiconductor layer.

Abstract: According to one embodiment, an original plate for imprint lithography has a first surface side having a patterned portion thereon. The patterned portion includes a groove having a bottom surface recessed from a first surface to a first depth, and a columnar portion on the bottom surface and protruding from the bottom surface to extend beyond the first surface. The original plate may be used to form replica templates by imprint lithography processes. The replica templates can be used in semiconductor device manufacturing processes or the like.

Abstract: A semiconductor manufacturing method includes forming a concave portion in a layer provided above a substrate from a top surface of the layer downwards, the layer including an insulation layer at least partially. The method includes forming a silicon film on an inner surface of the concave portion. The method includes exposing the silicon film to a raw material gas of metal and an inhibitor gas that inhibits growth of the metal at a first temperature, to replace a first portion of the silicon film located in an upper-end side portion of the concave portion with a first conductive film containing the metal. The method includes exposing the silicon film to the raw material gas and the inhibitor gas at a second temperature lower than the first temperature, to replace a second portion of the silicon film with a second conductive film containing the metal.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a word line, a bit line, a first transistor, a second transistor and a driver. The word line is electrically coupled to a gate of the memory cell. The bit line is electrically coupled to one end of the memory cell. The first transistor includes a first gate electrically coupled to the bit line. The second transistor is coupled to a first end of the first transistor. The driver is configured to apply a voltage to the first gate of the first transistor. In a read operation, the driver varies a voltage to be applied to the first gate of the first transistor based on a read voltage applied to the word line.

Abstract: According to one embodiment, a substrate processing apparatus includes: an inner tube extending in a first direction and configured to accommodate a plurality of substrates; an outer tube configured to surround the inner tube and provide an airtight sealed space; a nozzle disposed in the inner tube; a gas supply configured to supply a processing gas to the inner tube via the nozzle; at least one slit provided on a side surface of the inner tube facing the nozzle; and an exhaust port coupled to the outer tube. Along the first direction, an opening area of a central portion of the slit is larger than an opening area of end portions of the slit.

Abstract: According to a certain embodiment, the semiconductor device includes: an integrated circuit unit; a command control unit configured to execute command control for the integrated circuit unit on the basis of a command, an address, and/or data, each supplied from an outside; an internal state control unit configured to detect an operating state inside the integrated circuit unit, and to provide an internal state signal indicating a first state or a second state in accordance with the detected operating state; and an instruction rejection control unit configured to instruct the internal state control unit to compulsorily turn the internal state signal to the first state if an operation of the integrated circuit unit has not been completed even after a predetermined maximum monitoring time has elapsed, and to instructs the command control unit to reject an input/output operation of the command, the address, and/or the data.

Abstract: There is provided an inspection method that includes determining, as a reference blur component, the magnitude of the blur component of a range, the range being a range where a number of first inspection images among the plurality of inspection images falling within the range is the largest among a plurality of ranges. The inspection method includes correcting, based on the reference blur component, a second inspection image among the plurality of inspection images having the magnitude of the blur component falling outside the range. The inspection method includes comparing the first inspection image and the corrected second inspection image with a reference image, the first inspection image having the magnitude of the blur component falling within the predetermined range, the reference image being generated in advance for the measurement object.

Abstract: According to one embodiment, there is provided a memory card including a first surface, a second surface, and 1st to Nth terminal groups. The first surface includes first to Nth rows, where N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1st to Nth terminal groups are placed in the first to Nth rows. The 1st terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kth terminal group, where K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.

Abstract: A semiconductor device has a current controlled oscillation circuit configured to generate an oscillation clock in response to a current supplied, a first circuit configured to output a first signal when a phase of the oscillation clock is later than a phase of reception data, and to output a second signal when a phase of the oscillation clock is earlier than a phase of the reception data, and a current control circuit configured to control a current to be supplied to the current controlled oscillation circuit such that the number of times of output of the first signal from the first circuit matches the number of times of output of the second signal from the first circuit.

Abstract: In a semiconductor integrated circuit, a first oscillation circuit receives a first clock signal and outputs a second clock signal synchronized with the first clock signal in frequency and phase. A second oscillation circuit receives a control signal and outputs a third clock signal having a frequency corresponding to the received control signal. A detection circuit detects a frequency difference between the second clock signal and the third clock signal. A determination circuit determines whether a frequency locked state is established between the first clock signal and the second clock signal. A control circuit varies the control signal, such that the frequency difference decreases while the frequency locked state has not been established and increases after the frequency locked state is established.

Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.

Abstract: A semiconductor manufacturing apparatus includes a stage capable of holding thereon an interconnection substrate. A tool presses the interconnection substrate and a semiconductor chip against each other between the tool and the stage. The tool includes a main body portion that has a holding surface holding thereon the semiconductor chip. A first protruding portion is provided along an outer edge of the holding surface and protrudes from the holding surface toward the stage. A second protruding portion is provided outside of the first protruding portion along the outer edge of the holding surface and protrudes from the holding surface toward the stage. A groove portion is provided between the first protruding portion and the second protruding portion.

Abstract: A method performed by a controller of a solid-state drive (SSD) comprising splitting a logical to physical mapping table in a non-volatile semiconductor memory device of the SSD into a plurality of regions, each of the regions associated with a plurality of logical cluster addresses (LCAs), determining if the mapping table for each region contains an entry with a valid address, setting a validity status in a validity bit for a region of the plurality of regions if the mapping table for the region contains any mapped addresses, and storing the validity bit for each region in a validity bitmap table (VBT).

Abstract: According to an embodiment, a circuit in a semiconductor memory device sets threshold voltages of a plurality of memory cells such that two first distributions are formed in a first section on a lowest voltage side in 2N sections. After that, the circuit sets threshold voltages of the plurality of memory cells such that 2(1+M) second distributions are separately formed two by two. The circuit then sets 2N third distributions for the 2N sections.

Abstract: According to one embodiment, a memory system includes: a plurality of memory chips; a plurality of memory controllers; and a data encoding circuit configured to form a first group including a continuous plurality of first divided data among the user data, and generate a plurality of first page data. The memory controllers adjust a schedule of a write operation among the memory controllers and control a number of the write operations to be simultaneously executed. When at least one of the memory chips is in a busy state in a first read request, the memory controller connected to the memory chip in the busy state decodes the first divided data through erasure correction decoding processing using the first divided data read from the memory chip not in the busy state.