Abstract: According to one embodiment, when a command executed in a nonvolatile memory is an erase/program command and when a cumulative weight value satisfies a condition that a first input is selected as an input of high priority, a memory system suspends execution of the erase/program command by transmitting a suspend command to the nonvolatile memory. The memory system repeats executing an operation of starting the execution of one read command of the first input and an operation of updating the cumulative weight by using the weight associated with the read command until read command no longer exists in the first input or until the condition that the cumulative weight is larger than the first value is not satisfied, and resumes the execution of the suspended erase/program command.

Abstract: A semiconductor wafer according to an embodiment includes a support region facing a support member, an outer circumferential region positioned on an outer side of the support region, and an inner circumferential region positioned on an inner side of the support region. The outer circumferential region has a convex portion with a thickness protruded upward with respect to the inner circumferential region or a concave portion with a thickness recessed downward with respect to the inner circumferential region.

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a source line, word lines, a pillar, and a first member. The first member is provided to penetrate the source line. The first member includes a first portion which is far from the substrate, and a second portion which is near the substrate. The first member includes a first contact and a first insulating film. The first contact is provided to extend from the first portion to the second portion. The first contact is electrically connected to the substrate. The first insulating film insulates the source line from the first contact. The first member includes a stepped portion at a boundary part between the first portion and the second portion.

Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistance effect element including first and second magnetic layers each having a fixed magnetization direction, a third magnetic layer provided between the first and second magnetic layers, and having a variable magnetization direction, a first nonmagnetic layer between the first and third magnetic layers, and a second nonmagnetic layer between the second and third magnetic layers, and a switching element connected in series to the magnetoresistance effect element, changing from an electrically nonconductive state to an electrically conductive state when a voltage applied between two terminals is higher than or equal to a threshold voltage.

Abstract: A semiconductor memory device, includes: a stack including a wiring layer and an insulation layer alternately stacked in a first direction; a semiconductor layer including a first region overlapping with the insulation layer in a second direction, and a second region overlapping with the wiring layer in the second direction; an insulation region between the wiring layer and the second region; and a memory region on the opposite side of the second region from the wiring layer. The wiring layer is farther from the first region in the second direction than the insulation layer is. The second region has a part between the insulation layers in the first direction and protruding further toward the wiring layer than the first region in the second direction. The memory region has a face opposite to the second region and closer to the wiring layer in the second direction than the first region is.

Abstract: A semiconductor manufacturing apparatus according to an embodiment includes a first chamber, a second chamber, and a fluid pressure applier. The first chamber includes a first film and a first container. The first film is deformable. The first container contains an incompressible fluid that causes the first film to be deformed. The second chamber includes a second film and a second container. The second film faces the first film. The second film is deformable. The second container contains the incompressible fluid that causes the second film to be deformed. The fluid pressure applier is configured to apply a pressure to the incompressible fluid of each of the first chamber and the second chamber to cause the first film and the second film to be deformed in bonding a plurality of substrates to each other between the first film and the second film.

Abstract: A semiconductor memory device including: plural first conductive layers stacked on a substrate; plural second conductive layers each stacked between the first conductive layers; a pillar that extends in a stacking direction of the first and second conductive layers and forms plural memory cells at intersections of the first and second conductive layers in a region where first and second conductive layers are arranged; a first contact plug that extends in the stacking direction of the first and second conductive layers and is connected to the first conductive layers in the region where the first and second conductive layers are arranged; and a second contact plug that extends in the stacking direction of the first and second conductive layers and is connected to the second conductive layers in the region where the first conductive layers and second conductive layers are arranged.

Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

Abstract: A semiconductor memory device includes: a first wiring; a first memory transistor; a first transistor; a second memory transistor; a second transistor; a second wiring connected to a gate electrode of the first memory transistor; a third wiring; a first gate wiring connected to a gate electrode of the first transistor; a second gate wiring connected to a gate electrode of the second transistor; and a control circuit configured to execute an erase operation that selects the first or the second memory transistor. The control circuit controls a voltage of the first gate wiring to become larger than a voltage of the second wiring and controls a voltage of the second gate wiring to become larger than the voltage of the first gate wiring in the erase operation performed with the first memory transistor selected.

Abstract: A semiconductor manufacturing apparatus includes a stage capable of holding thereon an interconnection substrate. A tool presses the interconnection substrate and a semiconductor chip against each other between the tool and the stage. The tool includes a main body portion that has a holding surface holding thereon the semiconductor chip. A first protruding portion is provided along an outer edge of the holding surface and protrudes from the holding surface toward the stage. A second protruding portion is provided outside of the first protruding portion along the outer edge of the holding surface and protrudes from the holding surface toward the stage. A groove portion is provided between the first protruding portion and the second protruding portion.

Abstract: According to a certain embodiment, the semiconductor device includes: an integrated circuit unit; a command control unit configured to execute command control for the integrated circuit unit on the basis of a command, an address, and/or data, each supplied from an outside; an internal state control unit configured to detect an operating state inside the integrated circuit unit, and to provide an internal state signal indicating a first state or a second state in accordance with the detected operating state; and an instruction rejection control unit configured to instruct the internal state control unit to compulsorily turn the internal state signal to the first state if an operation of the integrated circuit unit has not been completed even after a predetermined maximum monitoring time has elapsed, and to instructs the command control unit to reject an input/output operation of the command, the address, and/or the data.

Abstract: According to one embodiment, there is provided a memory card including a first surface, a second surface, and 1st to Nth terminal groups. The first surface includes first to Nth rows, where N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1st to Nth terminal groups are placed in the first to Nth rows. The 1st terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kth terminal group, where K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.

Abstract: In a semiconductor integrated circuit, a first oscillation circuit receives a first clock signal and outputs a second clock signal synchronized with the first clock signal in frequency and phase. A second oscillation circuit receives a control signal and outputs a third clock signal having a frequency corresponding to the received control signal. A detection circuit detects a frequency difference between the second clock signal and the third clock signal. A determination circuit determines whether a frequency locked state is established between the first clock signal and the second clock signal. A control circuit varies the control signal, such that the frequency difference decreases while the frequency locked state has not been established and increases after the frequency locked state is established.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a word line, a bit line, a first transistor, a second transistor and a driver. The word line is electrically coupled to a gate of the memory cell. The bit line is electrically coupled to one end of the memory cell. The first transistor includes a first gate electrically coupled to the bit line. The second transistor is coupled to a first end of the first transistor. The driver is configured to apply a voltage to the first gate of the first transistor. In a read operation, the driver varies a voltage to be applied to the first gate of the first transistor based on a read voltage applied to the word line.

Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.

Abstract: A semiconductor device has a current controlled oscillation circuit configured to generate an oscillation clock in response to a current supplied, a first circuit configured to output a first signal when a phase of the oscillation clock is later than a phase of reception data, and to output a second signal when a phase of the oscillation clock is earlier than a phase of the reception data, and a current control circuit configured to control a current to be supplied to the current controlled oscillation circuit such that the number of times of output of the first signal from the first circuit matches the number of times of output of the second signal from the first circuit.

Abstract: According to an embodiment, a circuit in a semiconductor memory device sets threshold voltages of a plurality of memory cells such that two first distributions are formed in a first section on a lowest voltage side in 2N sections. After that, the circuit sets threshold voltages of the plurality of memory cells such that 2(1+M) second distributions are separately formed two by two. The circuit then sets 2N third distributions for the 2N sections.

Abstract: A method performed by a controller of a solid-state drive (SSD) comprising splitting a logical to physical mapping table in a non-volatile semiconductor memory device of the SSD into a plurality of regions, each of the regions associated with a plurality of logical cluster addresses (LCAs), determining if the mapping table for each region contains an entry with a valid address, setting a validity status in a validity bit for a region of the plurality of regions if the mapping table for the region contains any mapped addresses, and storing the validity bit for each region in a validity bitmap table (VBT).

Abstract: According to one embodiment, an original plate for imprint lithography has a first surface side having a patterned portion thereon. The patterned portion includes a groove having a bottom surface recessed from a first surface to a first depth, and a columnar portion on the bottom surface and protruding from the bottom surface to extend beyond the first surface. The original plate may be used to form replica templates by imprint lithography processes. The replica templates can be used in semiconductor device manufacturing processes or the like.

Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.