Abstract: A semiconductor die mounted between an X-lead frame and a support structure without bonding wires or straps. A power enhancement mode junction field effect transistor (JFET) die having a top surface defining a drain, and a bottom surface having a first metalized region defining a source and a second metalized region defining a gate, is positioned on a support structure. An X-lead frame is bonded to the support structure such that electrical contact is made with an external lead. Angular projections from the X-lead frame make contact with the top surface of the JFET, hold the die in place on the support structure, and form electrical continuity between the JFET drain and the external lead. A construction on the surface of the support structure is positioned directly under the source region on the bottom of the JFET die and forms electrical continuity between the JFET source and a second external lead.

Abstract: An enhancement mode JFET as a switching device in a buck-boost converter circuit combined with a single rectifier diode and an inductor. A control circuit coupled to the gate of the JFET switches the JFET between a current conducting state and a current blocking state. The ratio of converter output voltage to converter input voltage is determined by the ratio of JFET current blocking time to the sum of JFET conduction time and JFET blocking time. This pulse width modulation scheme is thus used to adjust the dc output voltage level.

Abstract: A programmable junction field effect transistor (JFET) with multiple independent gate inputs. A drain, source and a plurality of gate regions for controlling a conductive channel between the source and drain are fabricated in a semiconductor substrate. A first portion the gate regions are coupled to a first gate input and a second portion of the gate regions are coupled to a second gate input. The first and second gate inputs are electrically isolated from each other. The JFET may be programmed by applying a programming voltage to the first gate input and operated by applying a signal to the second gate input.

Abstract: JFET and MESFET structures, and processes of making same, for low voltage, high current and high frequency applications. The structures may be used in normally-on (e.g., depletion mode) or normally-off modes. The structures include an oxide layer positioned under the gate region which effectively reduces the junction capacitance (gate to drain) of the structure. For normally off modes, the structures reduce gate current at Vg in forward bias. In one embodiment, a silicide is positioned in part of the gate to reduce gate resistance. The structures are also characterized in that they have a thin gate due to the dipping of the spacer oxide, which can be below 1000 angstroms and this results in fast switching speeds for high frequency applications.

Abstract: A method for fabricating a junction field effect transistor (JFET) with a double dose gate structure. A trench is etched in the surface of a semiconductor substrate, followed by a low dose implant to form a first gate region. An anneal may or may not be performed after the low dose implant. A gate definition spacer is then formed on the wall the trench to establish the lateral extent of a second, high dose implant gate region. After the second implant, the gate is annealed. The double dose gate structure produced by the superposition of two different and overlapping regions provides an additional degree of flexibility in determining the ultimate gate region doping profile. A further step comprises using the gate definition spacer to define the walls of a second etched trench that is used to remove a portion of the p-n junction, thereby further reducing the junction capacitance.

Abstract: A semiconductor switching device or amplifier combined in parallel with one or more active devices defined as starter devices. A starter device is used to reduce the terminal voltage of a switching device or amplifier to a dc level below about 0.4 volts which will then allow the switching device to easily change between the on or conducting state and the off or non-conducting state. Three different starter devices are utilized. The first being a Bipolar Junction Transistor (BJT), the second a Metal Oxide Silicon Field Effect Transistor (MOSFET), and the third consisting of three normally off JFETs connected serially. Generally, a single starter device is coupled across the terminals of a semiconductor switching device or amplifier, but it is possible and sometimes advantageous to couple two or more starter devices in parallel. In a first case, a symmetrical, normally off or enhancement mode JFET is used as the switch or amplifier.

Abstract: JFET and MESFET structures, and processes of making same, for low voltage, high current and high frequency applications. The structures may be used in normally-on (e.g., depletion mode) or normally-off modes. The structures include an oxide layer positioned under the gate region which effectively reduces the junction capacitance (gate to drain) of the structure. For normally off modes, the structures reduce gate current at Vg in forward bias. In one embodiment, a silicide is positioned in part of the gate to reduce gate resistance. The structures are also characterized in that they have a thin gate due to the dipping of the spacer oxide, which can be below 1000 angstroms and this results in fast switching speeds for high frequency applications.

Abstract: A method for fabricating a junction field transistor for high-voltage applications. A lightly doped first epitaxial layer is formed on a highly doped substrate. A second epitaxial layer is deposited with a heavier dopant concentration than the first epitaxial layer. The second layer contains a control structure having a plurality of implanted gate regions and a source. A guard ring is formed to isolate the source and the control structure. The combination of the lightly doped first epitaxial layer and the guard ring enable the JFET to be operated with a breakdown voltage in excess of 100 volts. Multiple guard rings may be used to provide a breakdown voltage in excess of 150 volts.

Abstract: A method and structure for a composite trench fill for silicon electronic devices. On a planar silicon substrate having a first deposited layer of oxide and a second deposited layer of polysilicon, a trench is etched. Deposition and etch processes using a combination of oxide and polysilicon are used to fabricate a composite trench fill. The trench bottom and a lower portion of the walls are covered with oxide. The remaining portion of the trench volume is filled with polysilicon. The method may be used for junction field effect transistors (JFETs) and metal oxide semiconductor field effect transistors (MOSFETs).

Abstract: An apparatus and method for a semiconductor device with reduced gate capacitance. Specifically, an n-channel or p-channel junction field effect transistor (JFET) is described including an appropriately doped substrate forming a drain region, an epitaxial layer formed on top of the substrate, a control structure including a gate region implanted into the epitaxial layer, a source region sharing a p-n junction with the gate region, and an altered epitaxial region. The altered epitaxial region is formed by implanting either n− or p− dopants directly below the gate region of either the n-channel or p-channel JFET for widening a depletion region surrounding the gate region. The enlarged depletion region reduces the gate capacitance of the JFET between the gate and drain regions.

Abstract: A method for fabricating a junction field effect transistor (JFET) with a double dose gate structure. A trench is etched in the surface of a semiconductor substrate, followed by a low dose implant to form a first gate region. An anneal may or may not be performed after the low dose implant. A gate definition spacer is then formed on the wall the trench to establish the lateral extent of a second, high dose implant gate region. After the second implant, the gate is annealed. The double dose gate structure produced by the superposition of two different and overlapping regions provides an additional degree of flexibility in determining the ultimate gate region doping profile. A further step comprises using the gate definition spacer to define the walls of a second etched trench that is used to remove a portion of the p-n junction, thereby further reducing the junction capacitance.

Abstract: A protection device for integrated circuits. A complementary well is fabricated in a semiconductor substrate. An enhancement mode junction field effect transistor (JFET) is fabricated in the complementary well. An interface bonding pad is fabricated above the JFET. A source contact is also fabricated in the well. The gate and drain of the JFET are coupled to the interface bonding pad and the source of the JFET is coupled to the substrate.

Abstract: The present invention relates generally to electrical cascade circuits using normally-off junction field effect transistors (JFETs) which have low on-resistance for low voltage and high current density applications. Proper configuration of the normally-off JFETs allows for low voltage drop, low-on resistance, high current density and high frequency operations. More particularly, these cascade circuits are configured to provide amplification of an input signal and signal switching capabilities. In general two or more normally-off JFETs are coupled together on a substrate to create a desired characteristic. For a three terminal gate-controlled cascade amplification circuit, an input signal at the first JFET can realize a signal gain of 80 dB to 120 dB at the second JFET. A four terminal gate-controlled cascade switching circuit, comprised of two JFETs, switches on or off to regulate current flow through the second JFET.

Abstract: A semiconductor die mounted between an X-lead frame and a support structure without bonding wires or straps. A power enhancement mode junction field effect transistor (JFET) die having a top surface defining a drain, and a bottom surface having a first metalized region defining a source and a second metalized region defining a gate, is positioned on a support structure. An X-lead frame is bonded to the support structure such that electrical contact is made with an external lead. Angular projections from the X-lead frame make contact with the top surface of the JFET, hold the die in place on the support structure, and form electrical continuity between the JFET drain and the external lead. A construction on the surface of the support structure is positioned directly under the source region on the bottom of the JFET die and forms electrical continuity between the JFET source and a second external lead.

Abstract: A two terminal semiconductor circuit that can be used to replace the semiconductor diodes used as rectifiers in conventional DC power supply circuits. Three semiconductor circuits that can efficiently supply the DC currents required in both discrete and integrated circuits being operated at low DC supply voltages are disclosed. All three circuits have a forward or current conducting state and a reverse or non current conducting state similar to a conventional semiconductor diode.

Abstract: An apparatus and method for a semiconductor device with reduced gate capacitance. Specifically, an n-channel or p-channel junction field effect transistor (JFET) is described comprising an appropriately doped substrate forming a drain region, an epitaxial layer formed on top of the substrate, a control structure comprising a gate region implanted into the epitaxial layer, a source region sharing a p-n junction with the gate region, and an altered epitaxial region. The altered epitaxial region is formed by implanting either n− or p− dopants directly below the gate region of either the n-channel or p-channel JFET for widening a depletion region surrounding the gate region. The enlarged depletion region reduces the gate capacitance of the JFET between the gate and drain regions.

Abstract: A normally “off” enhancement mode junction field effect transistor (JFET) is disclose. The JFET has a low threshold voltage in the range of 0.2 to 0.3 volts and a low on resistance. The Drain-to-Source voltage drop is less than 0.1 volt at a drain current of 100 amperes.

Abstract: A matching circuit for coupling a conventional metal-oxide semiconductor field effect transistor (MOSFET) driver to the gate of a junction field effect transistor (JFET). A driver circuit optimized for driving a MOSFET is combined with a matching circuit to provide gate drive for a JFET. The matching circuit comprises a resistor and capacitor in parallel. For driving enhancement mode JFETs having a gate grid array structure and a pinch-off voltage greater than 0.4 volts, the range of resistor values is 10 to 200 ohms, and the range of capacitor values is 1 to 100 nF. For devices having a pinch-off voltage less than 0.4 volts, the range of resistor values is 100 to 2000 ohms. The matching circuit may further include a diode to provide a bias.

Abstract: This invention discloses rectifying circuits using normally “off” Junction Effect Transistor. By connecting the gate of the JFET to the higher bias terminal of the output coil of the transformer, the forward biased turn on function of the normally “off” JFETs can be achieved. Therefore, the normally “off” JFET can be used as synchronized zero voltage switching rectifier with very low voltage drop. Since normally “off” JFET is a majority carrier device, very high frequency response can be achieved. This kind of circuitry can replace the P-N junction and/or Schottky rectifiers especially when the supply voltage drops below three volts.

Abstract: A semiconductor switching device or amplifier combined in parallel with one or more active devices defined as starter devices. A starter device is used to reduce the terminal voltage of a switching device or amplifier to a dc level below about 0.4 volts which will then allow the switching device to easily change between the on or conducting state and the off or non-conducting state. Three different starter devices are utilized. The first being a Bipolar Junction Transistor (BJT), the second a Metal Oxide Silicon Field Effect Transistor (MOSFET), and the third consisting of three normally off JFETs connected serially. Generally, a single starter device is coupled across the terminals of a semiconductor switching device or amplifier, but it is possible and sometimes advantageous to couple two or more starter devices in parallel. In a first case, a symmetrical, normally off or enhancement mode JFET is used as the switch or amplifier.