Abstract: An enhancement mode JFET as a switching device in a boost converter circuit combined with a single rectifier diode and an inductor. A control circuit coupled to the gate of the JFET switches the JFET between a current conducting state and a current blocking state. The ratio of converter dc output voltage to converter dc input voltage is determined by the ratio of JFET conducting time to the sum of JFET conducting time and JFET blocking time. This pulse width modulation scheme is thus used to adjust the dc output voltage level. Limits on both frequency of operation and duty cycle result from slow switching speeds. Each time a device switches between states, a certain amount of energy is lost. The slower the device switching time, the greater the power loss in the circuit. The effects become very important in high frequency (fast switching) and/or high power circuits where as much as 50% of the losses are due to excessive switch transition time.

Abstract: A two terminal semiconductor circuit that can be used to replace the semiconductor diodes used as rectifiers in conventional DC power supply circuits. Three semiconductor circuits that can efficiently supply the DC currents required in both discrete and integrated circuits being operated at low DC supply voltages are disclosed. All three circuits have a forward or current conducting state and a reverse or non current conducting state similar to a conventional semiconductor diode. In a first configuration, an asymmetrical, enhancement mode, Junction Field Effect Transistor (JFET) is utilized as a two terminal device by connecting together the gate and source leads. The terminal voltage in the conducting state is considerably smaller than conventional semiconductor diodes. In a second configuration, an asymmetrical, enhancement mode, Junction Field Effect Transistor (JFET) is connected with a transformer such that the source and the drain serve as the two leads of a two terminal circuit.

Abstract: A four terminal full wave rectifier circuit that can be used as a pin for pin replacement for the full wave diode rectifier circuit commonly used in DC power supply circuits. Two full wave rectifier circuits that can efficiently supply the DC currents required in both discrete and integrated circuits being operated at low DC supply voltages are disclosed. Both circuits utilize two n-channel, enhancement mode Junction Field Effect Transistors (JFET) and two p-channel, enhancement mode Junction Field Effect Transistors to replace the rectifier diodes used in a conventional full wave rectifier circuit. The forward voltage drop across each JFET is considerably smaller than the forward voltage drop of a conventional rectifier. In a first configuration, the JFETs are all symmetrical about the source and drain leads. Starter devices are connected between source and drain leads and current limiting devices are in series with the gate leads.

Abstract: This invention discloses the concept of the integration of the four terminal switcher and the capacitor pairs for the DC to DC converter or power supplier. This invention can be built by IC process as the DC to DC converter or power supply alone or used as power supply or converter module or block for distributed power in the System-on-Chip. This invention discloses the basic structure of the DC to DC converter or power supply module on standard CMOS IC process and on SOI substrates. This basic structure of the DC to DC converter or power supply module provides high current and low voltage applications for future generations of ICs.

Abstract: A semiconductor package including a bottom leadframe having a bottom plate portion and a first terminal extending from the bottom plate portion, and a second terminal being co-planar with the first terminal. The semiconductor package also comprises a semiconductor power enhancement mode JFET die having a bottom surface and a top surface on which a first metalized region and a second metalized region are disposed. The bottom surface of the JFET die is coupled to the bottom plate of the leadframe. The semiconductor package also comprises a copper plate coupled to and spanning a substantial part of the first metalized region, and at least one beam portion sized and shaped to couple the copper plate portion to the second terminal such that it is electrically coupled to the source.

Abstract: This invention discloses the present invention discloses a junction field effect transistor (JFET) device supported on a substrate. The JFET device includes a gate surrounded by a depletion region. As the distance between the gates is large enough, there is a gap between the depletion regions surrounding adjacent gates. Depletion mode JFET transistor which is normally on is provided. The normally on transistors respond to negative bias applied to the gates to shut of the current path in the substrate. The current path in the substrate is normally available with a zero gate bias. As the distance between the gates is reduced, the JFET transistor is normally off because the depletion regions surround the gates shut of the current channel. The depletion region responding to a positive bias applied to the gate to open a current path in the substrate wherein the current path in the substrate is shut off when the gate is zero biased.

Abstract: An enhancement mode JFET as a switching device in a buck converter circuit combined with a single rectifier diode and an inductor. A control circuit coupled to the gate of the JFET switches the JFET between a current conducting state and a current blocking state. The ratio of converter dc output voltage to converter dc input voltage is determined by the ratio of JFET conducting time to the sum of JFET conducting time and JFET blocking time. This pulse width modulation scheme is thus used to adjust the dc output voltage level. Limits on both frequency of operation and duty cycle result from slow switching speeds. Each time a device switches between states, a certain amount of energy is lost. The slower the device switching time, the greater the power loss in the circuit. The effects become very important in high frequency (fast switching) and/or high power circuits where as much as 50% of the losses are due to excessive switch transition time.

Abstract: A semiconductor device efficiently providing the DC currents required in both discrete and integrated circuits operated at low DC supply voltages. The device disclosed in the present invention is an asymmetrical, enhancement mode, Junction Field Effect Transistor (JFET). The device consists of an epitaxial layer on the surface of a substrate, both of which are doped with the same polarity. The epitaxial layer has a graded doping profile with doping density increasing with distance from the substrate. A grill-like structure is constructed within the upper and lower bounds of, and extending throughout the length and width of the epitaxial layer, and is doped with a polarity opposite to that of the epitaxial layer. A first electrical connection made to the exposed side of the substrate is defined as the drain electrode. A second electrical connection made to the exposed surface of the epitaxial layer is defined as the source electrode.

Abstract: A four terminal full wave rectifier circuit that can be used as a pin for pin replacement for the full wave diode rectifier circuit commonly used in DC power supply circuits. Two full wave rectifier circuits that can efficiently supply the DC currents required in both discrete and integrated circuits being operated at low DC supply voltages are disclosed. Both circuits utilize two n-channel, enhancement mode Junction Field Effect Transistors (JFET) and two p-channel, enhancement mode Junction Field Effect Transistors to replace the rectifier diodes used in a conventional full wave rectifier circuit. The forward voltage drop across each JFET is considerably smaller than the forward voltage drop of a conventional rectifier. In a first configuration, the JFETs are all symmetrical about the source and drain leads. Starter devices are connected between source and drain leads and current limiting devices are in series with the gate leads.

Abstract: Junction Field Effect Transistor (JFET) offers fast switching speed than bipolar transistor since JFET is a majority carrier device. This invention comprises two normally “off” JFETs, one in N-channel and one in P-channel to form Complementary Junction Field Effect Transistors for high speed, low voltage and/or high current applications. The discrete device structure is disclosed in this invention. The integrated Complementary Junction Field Effect Transistors structure processed in standard CMOS process is disclosed in this invention. A vertical gate structure of Complementary Junction Field Effect Transistors is disclosed. Complementary Junction Field Effect Transistors structure is also disclosed in SOI substrate.

Abstract: This invention discloses a switching device that switches an array of capacitors in series configuration in charging condition and switches an array of capacitors in parallel configuration in discharging condition for voltage stepdown DC to DC converter. This switcher can also be used for the voltage stepup conversion by charging an array of capacitors in the parallel configuration and discharging an array of capacitors in series configuration. The novel structure of this invention is to use the normally “offs” JFETs with both N-chamel and P-channel that provide low on resistance of sub-milliohm and large current for high efficiency energy conversions. This invention discloses the integrated structure of the switcher. The switcher built in common CMOS IC process is also disclosed in this invention.

Abstract: This invention discloses the concept of the integration of the four terminal switcher and the capacitor pairs for the DC to DC converter or power supplier. This invention can be built by IC process as the DC to DC converter or power supply alone or used as power supply or converter module or block for distributed power in the System-on-Chip. This invention discloses the basic structure of the DC to DC converter or power supply module on standard CMOS IC process and on SOI substrates. This basic structure of the DC to DC converter or power supply module provides high current and low voltage applications for future generations of ICs.

Abstract: This invention discloses the present invention discloses a junction field effect transistor UFET) device supported on a substrate. The JFET device includes a gate surrounded by a depletion region. As the distance between the gates is large enough, there is a gap between the depletion regions surrounding adjacent gates. Depletion mode JFET transistor which is normally on is provided. The normally on transistors respond to negative bias applied to the gates to shut of the current path in the substrate. The current path in the substrate is normally available with a zero gate bias. As the distance between the gates is reduced, the JFET transistor is normally off because the depletion regions surround the gates shut of the current channel. The depletion region responding to a positive bias applied to the gate to open a current path in the substrate wherein the current path in the substrate is shut off when the gate is zero biased.