Abstract: A storage system and method for interleaving a plurality of logical sectors in the storage system is disclosed. The method includes: dividing each logical sector into a predetermined number of slices; sequentially indexing the logical sectors, wherein each logical sector is identified by a logical sector index; sequentially indexing the predetermined number of slices in each logical sector, wherein each slice of the predetermined number of slices is identified by a slice index within each logical sector; and interleaving the logical sectors according to a slice interleaving process. The interleaving step further includes: a) identifying a first indexed slice of a first indexed logical sector as an initial slice; and b) identifying a subsequent slice by advancing the slice index to a subsequent index in the slice index sequence and advancing the logical sector index to a subsequent index in the logical sector index sequence.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to data processing including operational marginalization capability.

Abstract: An apparatus having a circuit and a decoder is disclosed. The circuit is configured to (i) adjust an initial one of a plurality of reference voltages in a read channel of a memory by shifting the initial reference voltage an amount toward a center of a window and (ii) read a codeword from the memory a number of times. The window bounds a sweep of the reference voltages. Each retry of the reads uses a respective reference voltage from a pattern of the reference voltages. The pattern is symmetrically spaced about the initial reference voltage. The pattern fits in the window. The decoder is configured to generate read data by performing an iterative decoding procedure on the codeword based on the reads.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for detecting a sync mark with a ratio-adjustable detection system.

Abstract: A memory interleaving apparatus includes first and second interleavers. The first interleaver selectively interleaves information stored in a first memory in response to a sector select signal. The second interleaver selectively interleaves information stored in a second memory in response the sector select signal. The first interleaver is coupled with the second interleaver. A memory interleaving system includes an interleaver and a storage device. The interleaver is associated with a first sector size and a second sector size. The interleaver selectively interleaves information stored in a first memory and/or a second memory in response to a sector select signal. The storage device selectively provides the first masking seed and/or a second masking seed to the interleaver in response to the sector select signal. Corresponding methods are also disclosed.

Abstract: Methods and structure for emulating wide ports at an expander are provided. An exemplary system includes a Serial Attached Small Computer System Interface (SAS) expander. The expander includes a plurality of physical links, and a controller. The controller is able to identify a physical link coupled with a device, to generate a plurality of virtual physical links that are configured as a virtual wide port coupled with the device, and to present the virtual wide port at the expander in place of the physical link.

Abstract: Various embodiments of the present invention provide pipelined vectoring-mode CORDICS including a coordinate converter operable to yield a converted vector based on an input vector, wherein an x coordinate value of the converted vector is positive, a y coordinate value of the converted vector is positive, and the x coordinate value is greater than or equal to the y coordinate value, a pipeline of vector rotators operable to perform a series of successive rotations of the converted vector to yield a rotated vector and to store rotation directions of the series of successive rotations, and at least one lookup table operable to yield an angle of rotation based on the rotation directions.

Abstract: Embodiments of the present inventions are related to systems and methods for decoding data in an LDPC decoder with flexible saturation levels for variable node probability values.

Abstract: An apparatus for layered low density parity check decoding includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived data values based on check node to variable node messages. The check node processor includes an intermediate message generator circuit operable to generate intermediate check node messages, a shift register based memory operable to store the intermediate check node messages, and at least one check node to variable node message generator circuit operable to generate the check node to variable node messages based on the intermediate check node messages from the shift register based memory.

Abstract: A storage system includes a storage medium operable to maintain a data set, a read/write head assembly operable to write the data set to the storage medium and to read the data set from the storage medium, a multi-level encoder operable to encode the data set at a plurality of different code rates before it is written to the storage medium, and a multi-level decoder operable to decode the data set retrieved from the storage medium and to apply decoded values encoded at a lower code rate when decoding values encoded at a higher code rate.

Abstract: A memory device includes a memory array comprising a plurality of memory cells, and control circuitry coupled to the memory array. The control circuitry comprises at least one dummy memory cell, a feedback-based controller having inputs coupled to respective internal nodes of the dummy memory cell, and write signal generation circuitry coupled to the feedback-based controller and configured to provide one or more write signals for controlling writing of data to portions of the memory array. The feedback-based controller generates a reset signal for application to a reset input of the write signal generation circuitry at least in part as a function of a logic level transition delay of a selected one of the first and second internal nodes of the dummy memory cell.

Abstract: An apparatus for decoding data includes a variable node processor, a check node processor, and a field transformation circuit. The variable node processor is operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages. The check node processor is operable to generate the check node to variable node messages and to calculate checksums based on variable node to check node messages. The variable node processor and the check node processor comprise different Galois fields. The field transformation circuit is operable to transform the variable node to check node messages from a first of the different Galois fields to a second of the Galois fields.

Abstract: A data encoding system includes a data encoder circuit operable to encode each of a number of data sectors with a component matrix of a low density parity check code matrix and to yield an output codeword. The data encoder circuit includes a syndrome calculation circuit operable to calculate and combine syndromes for the data sectors.

Abstract: An apparatus for reading a flash memory includes a read controller operable to read the flash memory to yield read patterns, a likelihood generator operable to map the read patterns to likelihood values, a decoder operable to decode the likelihood values, a data state storage operable to retrieve the likelihood values for which decoding failed, and a selective dampening controller operable to select at least one dampening candidate from among the likelihood values for which decoding failed, to dampen the likelihood values of the at least one dampening candidate to yield dampened likelihood values, and to provide the dampened likelihood values to the decoder for decoding.

Abstract: An apparatus for reading a non-volatile memory includes a tracking module operable to calculate means and variances of voltage level distributions in a non-volatile memory and to calculate at least one reference voltage to be used when reading the non-volatile memory based on the means and variances, a likelihood generator operable to calculate at least one other reference voltage to be used when reading the non-volatile memory, wherein the at least one other reference voltage is based at least in part on a predetermined likelihood value constellation, and to map read patterns from the non-volatile memory to likelihood values, and a read controller operable to read the non-volatile memory using the at least one reference voltage and the at least one other reference voltage to yield the read patterns.

Abstract: An apparatus having a device and a circuit is disclosed. The device has a plurality of bit-lines and is configured to store a codeword. The circuit is configured to (i) receive the codeword from the device, (ii) generate a syndrome by performing a portion less than all of an iterative decoding procedure on the codeword and (iii) generate a map of defects according to the syndrome. Each of a plurality of bits in the map corresponds to a respective one of the bit-lines.

Abstract: Mis-programming of MSB data in flash memory is avoided by maintaining a copy of LSB page data that has been written to flash memory and using the copy rather than the LSB page data read out of the flash cells in conjunction with the MSB values to determine the proper reference voltage ranges to be programmed into the corresponding flash cells. Because the copy is free of errors, using the copy in conjunction with the MSB values to determine the proper reference voltage ranges for the flash cells ensures that mis-programming of the reference voltage ranges will not occur.

Abstract: An apparatus includes a memory and a processor. The memory may be configured to store at least a portion of a multi-level tree representation of an ordered multi-field rule-based classification list. The tree representation includes at least one non-leaf level and one or more leaf levels. Each entry in the at least one non-leaf level contains a count value indicating a number of rules having a matching field. Entries in at least one of the one or more leaf levels include rule pointers arranged in priority order. The processor may be configured to incrementally insert or delete rules, while preserving ordering semantics of the tree representation.

Abstract: An apparatus having one or more lookup tables and a decoder is disclosed. The lookup tables are configured to store a plurality of sets of values of log likelihood ratios. The decoder is configured to (i) receive a codeword read from a memory, (ii) receive an initial one of the sets from the lookup tables and (iii) generate read data by decoding the codeword based on the values.

Abstract: A metal substrate with a slot therein forms a slot antenna, the slot having a major axis and a minor axis. A dielectric layer has a plurality of terminals disposed on or in the dielectric layer and the layer is attached on one surface of the substrate. The terminals of a non-linear device, such as a diode, are connected to corresponding terminals of the dielectric layer. The non-linear device is positioned proximate the slot and is substantially aligned with a minor axis of the slot. A transmission line feeds an RF signal to the non-linear device that in turn frequency multiplies the RF signal to an RF signal that is radiated by the slot antenna. The dielectric layer is positioned in the slot such that the radiated RF signal has a desired output power. A protective layer is applied to the other surface of the substrate to cover the slot.