Abstract: Described embodiments provide for, in a clock and data recovery (CDR) circuit, detection of loss of acquisition and CDR restarting with corrective integral accumulator register seeding and gearshift restarting. In described embodiments, a mechanism is employed to cause faster loss of lock condition if the CDR circuit directed on an incorrect acquisition trajectory, actual loss of CDR lock is then detected, and CDR acquisition is recovered with corrective integral accumulator seeding.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for determining a down track distance between two or more read heads on a read/write head assembly.

Abstract: Level shifters are disclosed for high performance sub-micron IC designs. One embodiment is a level shifting device that comprises a first input circuit that toggles a first internal signal between a logical zero of a first voltage range and a logical one of a second voltage range based on an input data signal and an output data signal, and a second input circuit that toggles a second internal signal between a logical zero of the second voltage range and a logical one of the first voltage range based on the input data signal and the output data signal. An output circuit of the device toggles the output data signal between a logical zero of the second voltage range and a logical one of the second voltage range based on the first internal signal, the second internal signal, and a compliment of the input data signal.

Abstract: A process to form metal pillars on a flip-chip device. The pillars, along with a layer of solder, will be used to bond die pads on the device to respective substrate pads on a substrate. A photoresist is deposited over the device and a first set of die pads on the device are exposed by forming openings of a first diameter in the photoresist. Pillars of the first diameter are formed by electroplating metal onto the exposed die pads. Then a second photoresist deposited over the first photoresist covers the pillars of the first diameter. Openings of a second diameter are formed in the first and second photoresists to expose a second set of die pads. Pillars of the second diameter are formed by electroplating metal onto the exposed die pads. The photoresists are then removed along with conductive layers on the device used as part of the plating process.

Abstract: An apparatus includes a hit bitline driver circuit and an equalization control circuit. The hit bitline driver circuit may be configured to drive a pair of hit bitlines responsive to a search bit. The equalization control circuit may be configured to transfer charge from one hit bitline of the pair to the other hit bitline of the pair in response to the search bit changing state.

Abstract: Systems, methods, devices and circuits for data amplification, and more particularly systems and methods for characterizing distortion introduced during data amplification. In some cases, an amplifier modeling circuit is discussed that receives a preamplifier status input from a preamplifier circuit; applies a vector fitting algorithm to the preamplifier status to yield a pole value; determines that the pole value is greater than unity; and replaces the pole value with an inverse of the pole value when the pole value is greater than unity.

Abstract: Methods and systems for generating data transformations to improve ROM yield and programming time. A bit flip register can be configured in association with the ROM and a binary string can be read into the bit flip register on reset. Subsequently, data output from the ROM can be selectively complemented utilizing a content of the bit flip register and the content of the bit flip register can be programmed into the ROM in order to reduce programming time for each ROM. A defective cell can be tolerated by selectively flipping a column with respect to the defective cell to improve yield. A built-in self-test (BIST) engine that generates addresses up to and including content of an address limiting register can be employed to limit the ROM access to a programmed part during testing in order to tolerate defects in any unused location.

Abstract: A process to form metal pillars on a flip-chip device. The pillars, along with a layer of solder, will be used to bond die pads on the device to respective substrate pads on a substrate. A photoresist is deposited over the device and first openings in the photoresist are formed. Metal layers are formed by electroplating metal into the first openings for a first time period. Then the photoresist is patterned to form second openings having a smaller diameter than the first openings. Narrow pillars are formed by electroplating metal into the second openings for a second time period during which the metal is also added to the metal layers in the first openings to form wide pillars having substantially the same height as the narrow pillars. The photoresist is then removed along with conductive layers on the device used as part of the plating process.

Abstract: Systems and methods for resource allocation for a large sector format processing may include, but are not limited to, operations for: determining non-convergence of a magnetic disc sub-sector of a first magnetic disc sector within a processing time frame allocated to the magnetic disc sub-sector; determining a convergence of a second magnetic disc sector occurring in less time than a processing time frame allocated to the second magnetic disc sector; and processing the magnetic disc sub-sector during a portion of the processing time frame allocated to the second magnetic disc sector remaining after processing of the second magnetic disc sector.

Abstract: An N-way parallel, unrolled decision feedback equalizer for a SerDes receiver can convert between four-tap PAM-2 and two-tap PAM-4 mode, maximizing hardware through the use of mode control multiplexers. Each of N interleaved parallel branches includes an ISI correction stage for generating a partial result approximating intersymbol interference and comparing the partial result to a threshold, a carry look-ahead stage for generating a second partial result based in part on previously generated partial results, and a decision feedback stage for generating a final decision based on previous branches. Mode control multiplexers can select from PAM-2 and PAM-4 operating modes, PAM-2 and MAP-4 inputs at various stages, or from single-bit PAM-2 and two-bit PAM-4 outputs. ISI correction can additionally be reformulated to incorporate comparing raw input symbols to a combination of approximated ISI and a threshold.

Abstract: An apparatus having a circuit and an interface to a nonvolatile memory is disclosed. The circuit is configured to (i) read a plurality of bits in a read channel of the nonvolatile memory. The bits are encoded with a polar code. The circuit is also configured to (ii) generate a plurality of probabilities based on a plurality of log likelihood ratio values of the read channel and (iii) decode the bits based on the probabilities.

Abstract: Systems and methods for magnetoresistive asymmetry estimation may include, but are not limited to, operations for: receiving a magnetic read head transducer output; computing a mean value of the magnetic read head transducer output; computing a median value of the magnetic read head transducer output; and applying a correction coefficient to a magnetic read head detector input according to at least the mean value of the magnetic read head transducer output and the median value of the magnetic read head transducer output.

Abstract: SRAM devices are disclosed that utilize write assist circuits to improve the logical transitions of bit lines. In one embodiment, an SRAM device includes a pair of complimentary bit lines traversing a memory cell array for writing data to memory cells. The bit lines have a first end and a second end. A pair of complimentary write drivers is proximate to the first end of the bit lines that writes to the bit lines. A write assist circuit is proximate to the second end of the bit lines that receives a pre-charge signal to assist the write drivers in transitioning the bit lines from a logical zero state to a logical one state. The write assist circuit also receives a boost signal to assist the write drivers in transitioning the bit lines from a logical one state to a logical zero state.

Abstract: A method of mitigating an effect of track misregistration on read performance in a system comprising an array-reader includes determining an estimated off-track condition, selecting translation coefficients based on the estimated off-track condition, determining updated equalizer coefficients by applying the translation coefficients to native equalizer coefficients, and applying the updated equalizer coefficients to signals received from the array-reader to output a read signal.

Abstract: Described embodiments provide for de-coupling between adaptation of decision feedback equalizer (DFE) filter taps and transmitter (TX) post cursor filtering in group delay (GD)-based adaptation. Consequently, an excessive build-up of transmitter post cursor effects and its excessive equalization cancellation by the DFE may be substantially reduced or eliminated. By breaking this coupling, a transmitter does not over equalize a signal, the DFE does not attempt to “undo” the over equalization, and a variable gain amplifier (VGA) in the receiver front end data path generally does not apply gain to amplify the signal back again due to the reduced DC level. GD-based TX post cursor adaptation may reduce over equalization effect and hence save power and increase performance by not over equalizing the signal.

Abstract: A non-binary layered low density parity check decoder includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on normalized check node to variable node messages and on normalized decoder inputs, and to output normalized decoded values, and a check node processor operable to generate the check node to variable node messages based on normalized variable node to check node messages.

Abstract: In described embodiments, process, voltage, temperature (PVT) compensation in a serializer/deserializer (SerDes) device employs a closed loop adaptation compensation that is incorporated into the SerDes receiver adaptation process. A detection method, where the adapted decision feedback equalizer (DFE) target level (e.g., tap H0) is monitored, employs this DFE target level when implementing a closed loop variable gain amplifier adaptation. The DFE target level in conjunction with the VGA level is used to control the PVT setting to maintain target SerDes data path gain by detecting aPVT corner condition. The detected PVT corner condition is employed to generate a control signal to further adjust the LEQ and DFE data path differential pair gain as required by the PVT condition.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for reporting a synchronization indication and for applying a synchronization window. As an example, a system is discussed that includes: a head assembly including a first read head and a second read head; a down track distance calculation circuit operable to calculate a down track distance between the first read head and the second read head; and a synchronization mark detection circuit. The synchronization mark detection circuit is operable to: assert a synchronization mark window based at a location based at least in part on the down track distance; query a first data set derived from the first read head for a synchronization mark occurring within the synchronization mark window; and query a second data set derived from the second read head for the synchronization mark occurring within the synchronization mark window.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for processing servo data using two or more sensing heads.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for determining a down track distance between two or more read heads on a read/write head assembly.