Abstract: The present invention provides a control method of an electronic device, wherein the control method includes the steps of: using a first beacon setting to transmit beacons; if a wireless communication state of the electronic device satisfies a condition, using a second beacon setting to transmit beacons; wherein the first beacon setting and the second beacon setting have different beacon periods or different payload sizes.

Abstract: Various examples pertaining to extremely-high-throughput (EHT) error recovery in synchronous multiple-frame transmission in wireless communications are described. A multi-link device (MLD) detects a failure related to either or both of a first frame exchange sequence on a first link or a second frame exchange sequence on a second link. In response to the detecting, the MLD adjusts a timing of either or both of a first subsequent transmission on the first link and a second subsequent transmission on the second link to align the first and second subsequent transmissions.

Abstract: Various examples pertaining to efficient trigger-based (TB) multi-user (MU) uplink (UL) transmissions in wireless local area networks (WLANs) are described. A stations (STA) receives a trigger frame from an access point (AP), with the trigger frame assigning one or more resource units (RUs) corresponding to one or more subchannels of a plurality of subchannels. The STA then performs a transmission using the assigned one or more RUs responsive to receiving the trigger frame. In an event that at least one subchannel of the plurality of subchannels is detected as being busy, the one or more subchannels may include a subset (e.g., some but not all) of the plurality of subchannels.

Abstract: An electronic device and a method for reducing power consumption of signal transmission in the electronic device are provided. The electronic device may include a source circuit, a destination circuit, at least one transmission wire and at least one resonance wire, wherein the at least one transmission wire is coupled between at least one output terminal of the source circuit and at least one input terminal of the destination circuit, and the at least one resonance wire is coupled to the at least one input terminal of the destination circuit and is routed along the at least one transmission wire. In specific, the source circuit is configured to output an oscillation signal having an oscillation frequency, the destination circuit is configured to receive the oscillation signal, wherein the at least one transmission wire is configured to transmit the oscillation signal from the source circuit to the destination circuit.

Abstract: A semiconductor structure includes a first substrate having a wiring structure, a first semiconductor die disposed on the first substrate, and a multi-terminal capacitor structure disposed on the first substrate. The multi-terminal capacitor includes a second substrate, an insulating layer disposed over the second substrate, a first multi-terminal capacitor disposed over the insulating layer and electrically coupled to the first semiconductor die through the wiring structure, and a second multi-terminal capacitor disposed over the insulating layer and electrically coupled to the second semiconductor die through the wiring structure, wherein the first multi-terminal capacitor and the second multi-terminal capacitor are electrically isolated from the second substrate.

Abstract: A frequency calibration (FCAL) circuit and a method for calibrating an oscillation frequency of a controllable oscillator are provided. The FCAL circuit includes the controllable oscillator, a divider, a time-to-digital converter (TDC) and a calibration logic. The controllable oscillator generates a controllable oscillation clock according to a calibration code. The divider divides the oscillation frequency of the controllable oscillation clock by a predetermined divisor to generate a divided clock. The TDC converts a first period between first edges of a reference clock and the divided clock into a first period code and converts a second period between second edges of the reference clock and the divided clock into a second period code. The calibration logic compares the first period code and the second period code to generate a comparison result for determining whether the first period is greater or less than the second period, and accordingly controls the calibration code.

Abstract: An image reconstructing method for generating an output image according to an input image and a target EV is disclosed. The image reconstructing method comprises: (a) extracting at least one first feature map of the input image; (b) synthesizing at least one second feature map with the target EV to generate at least one third feature map; (c) performing affine brightness transformation to the third feature map to generate fourth feature maps; and (d) synthesizing the input image with the fourth feature maps to generate the output image. An image generation training method with a cycle training is also disclosed.

Abstract: A wireless device control circuit with modularized internal circuit architecture and associated wireless communications device are provided. The wireless device control circuit may include a first digital processing circuit and a second digital processing circuit. The first digital processing circuit is arranged to perform first digital processing corresponding to a first predetermined radio frequency band for the wireless communications device, the first digital processing including common processing and a first additional processing. The second digital processing circuit is arranged to perform second digital processing corresponding to a second predetermined radio frequency band for the wireless communications device, the second digital processing including the common processing and a second additional processing.

Abstract: A semiconductor structure includes several semiconductor stacks over a substrate, and each of the semiconductor stacks extends in a first direction, wherein adjacent semiconductor stacks are spaced apart from each other in a second direction, which is different from the first direction. Each of the semiconductor stacks includes channel layers above the substrate and a gate structure across the channel layers. The channel layers are spaced apart from each other in the third direction. The gate structure includes gate dielectric layers around the respective channel layers, and a gate electrode along sidewalls of the gate dielectric layers and a top surface of the uppermost gate dielectric layer. The space in the third direction between the two lowermost channel layers is greater than the space in the third direction between the two uppermost channel layers in the same semiconductor stack.

Abstract: A phase error compensation circuit and a method for compensating a phase error between a reference clock and a feedback clock are provided. The phase error compensation circuit includes a first programmable delay circuit, a second programmable delay circuit and at least one swapping circuit. The first programmable delay circuit provides a first delay. The second programmable delay circuit provides a second delay. At a present cycle, the first delay is unchanged, wherein the swapping circuit applies the first delay to the feedback clock for generating a compensated feedback clock and applies the second delay to the reference clock for generating a compensated reference clock. At a next cycle, the second delay is unchanged, where the swapping circuit applies the second delay to the feedback clock for generating the compensated feedback clock and applies the first delay to the reference clock for generating the compensated reference clock.

Abstract: A method for implicitly signaling a transmit (Tx) switching configuration includes: configuring a first signaling message to indicate a band combination of a plurality of bands; and sending the first signaling message, wherein the Tx switching configuration is implicitly signaled by an order of the plurality of bands of the band combination indicated by the first signaling message.

Abstract: The present invention provides a circuitry of a biopotential acquisition system comprising an input node, an ETI transmitter and an ADC. The input node is coupled to an electrode of the biopotential acquisition system, and the electrode is used to be in contact with a human body. The ETI transmitter is configured to generate a transmitter signal to the input node. The ADC is coupled to the input node, and is configured to process an input signal from the input node to generate a digital signal, wherein each of the input signal and the digital signal comprises components of an ECG signal and an ETI signal.

Abstract: A management circuit is coupled to multiple processor cores for performing current suppression. The management circuit includes a detection circuit and a throttle signal generator. The detection circuit is operative to receive an activity signal from each processor core, and estimate a total current consumed by the plurality of processor cores based on activity signals. The activity signal indicates a current index proportional to current consumption of the processor core in a given time period. The throttle signal generator is operative to assert or de-assert throttle signals to the processor cores, one processor core at a time, based on one or more metrics calculated from the total current.

Abstract: A method for predicting user's intent is provided. The method is performed by a computing device and includes: receiving spatial information and acceleration data from a portable device and a wearable device worn by a user, wherein the wearable device and the portable device measure the spatial information between each other via UWB when either the wearable device or the portable device detects that an activity of the user or a motion status of either the wearable device or the portable device has changed based on the acceleration data measured by accelerometers in the wearable device and the portable device; identifying a behavior of the user using the wearable device and the portable device and predicting user's intent based on the spatial information and the acceleration data; and transmitting a notification signal to the wearable device to notify the user of user's intent.

Abstract: A system performs adaptive thermal ceiling control at runtime. The system includes computing circuits and a thermal management module. When detecting a runtime condition change that affects power consumption in the system, the thermal management module determines an adjustment to the thermal ceiling of a computing circuit, and increases the thermal ceiling of the computing circuit according to the adjustment.

Abstract: Methods and apparatus are provided for UE-triggered handover and early preparation with coexistence of the network-triggered handover. In one novel aspect, the UE is configured early measurement report configuration, receives an early handover command from the serving base station with a handover candidate cell list, monitors handover triggering conditions for each candidate cell on the handover candidate cell list based on a UE-triggered handover configuration and performs the UE-triggered handover to a candidate cell when the corresponding triggering condition is met for the candidate cell. In one embodiment, the UE receives a network-triggered handover command to a target cell, suspends the UE-triggered handover configuration and performs the network-triggered handover to the target cell. The UE discards the UE-triggered handover configuration upon success of the network-triggered handover and resumes the UE-triggered handover configuration upon failure of the network-triggered handover.

Abstract: The present invention provides a control method of a wireless communication module having a first link and a second link. The control method includes the steps of: obtaining a first timestamp of a first reference point corresponding to a first PPDU, wherein the first PPDU is transmitted on a channel corresponding to the first link; obtaining a second timestamp of a second reference point corresponding to the second link, wherein the second reference point is a slot boundary, a transmission end or a reception end; determining a length of a second PPDU according to the first timestamp and the second timestamp, to make an end of the second PPDU is aligned to an end of the first PPDU; and generating the second PPDU according to the determined length of the second PPDU, and transmitting the second PPDU after the second reference point.

Abstract: The present invention provides a control method of a wireless communication module, wherein the control method includes the steps of: obtaining a plurality of media access control protocol data units (MPDUs), wherein each MPDU comprises a packet mark; aggregating the plurality of MPDUs to generate a physical layer protocol data unit (PPDU); and determining a final transmission rate setting according to statistics of the packet marks of the plurality of MPDUs, wherein the final transmission rate setting is used for a wireless transmission of the PPDU.

Abstract: The present invention provides a control method of an electronic device, wherein the control method includes the steps of: establishing pre-linked buffers in a memory; wirelessly receiving a frame; generating a plurality of MPDUs according to the frame, wherein each of the MPDUs comprises at least one MSDU; writing the MSDUs of the plurality of MPDUs into the pre-linked buffers, wherein each buffer is configured to store one MSDU; generating a command to read in-order MPDUs from the memory if the memory has the in-order MPDUs.

Abstract: The techniques described herein relate to systems, apparatus, articles of manufacture, and methods for optimum loop gain calibration for clock data recovery and phase locked loop. An example apparatus includes a phase detector with a phase detector output and configured to generate an error signal representative of a difference between an input signal and a feedback signal. The apparatus further includes a calibrator circuit with a calibrator input coupled to the phase detector output and configured to determine correlation value associated with the error signal, and determine a gain value based on an adjustment of an absolute value of the correlation value by a pseudorandom binary sequence signal.